Visible to Intel only — GUID: sam1403482514368
Ixiasoft
Visible to Intel only — GUID: sam1403482514368
Ixiasoft
5.2.2. IOPLL Parameter Values for External PLL Mode
Parameter | outclk0 (Connects as outclk_periph[0] to the ext_outclk_periph[0] port of LVDS SERDES IP) |
outclk1 (Connects as outclk_periph[1] to the ext_outclk_periph[1] port of LVDS SERDES IP) |
VCO Frequency (Connects as phout[7:0] to the ext_phout[7:0] port of LVDS SERDES IP |
---|---|---|---|
Frequency | data rate |
data rate/16 |
Use the value recommended by the LVDS and IOPLL IPs |
Phase shift | 180° |
180°/16 = 11.25 |
— |
Duty cycle | 50% |
50% |
— |
The calculations for phase shift, using the RSKM equation, assume that the input clock and serial data are edge aligned. Introducing a phase shift of 180° to sampling clock (outclk0) ensures that the input data is center-aligned with respect to the outclk0, as shown in the following figure.
Parameter | outclk0 (Connects as outclk_periph[0] to the ext_outclk_periph[0] port of LVDS SERDES IP) |
outclk1 (Connects as outclk_periph[1] to the ext_outclk_periph[1] port of LVDS SERDES ) Not required for the soft-CDR receiver. |
outclk27 (Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_pll_1_outclock2 port of LVDS SERDES IP) |
VCO Frequency (Connects as phout[7:0] to the ext_phout[7:0] port of LVDS SERDES IP) |
---|---|---|---|---|
Frequency | data rate |
data rate/16 |
data rate/serialization factor |
Use the value recommended by the LVDS and IOPLL IPs |
Phase shift | 180° |
180°/16 = 11.25 |
180°/serialization factor (outclk0 phase shift divided by the serialization factor) |
— |
Duty cycle | 50% |
50% |
50% |
— |
Parameter | outclk0 (Connects as outclk_periph[0] to the ext_outclk_periph[0] port of LVDS SERDES IP) |
outclk1 (Connects as outclk_periph[1] to the ext_outclk_periph[1] port of LVDS SERDES IP) Not required for the soft-CDR receiver. |
VCO Frequency (Connects as phout[7:0] to the ext_phout[7:0] ports of LVDS SERDES IP) |
---|---|---|---|
Frequency | data rate |
data rate/16 |
data rate |
Phase shift | 180° |
180°/16 = 11.25 |
— |
Duty cycle | 50% |
50% |
— |
Parameter | outclk0 (Connects as outclk_periph[0] to the ext_outclk_periph[0] port of LVDS SERDES IP) |
outclk1 (Connects as outclk_periph[1] to the ext_outclk_periph[1] port of LVDS SERDES IP) |
VCO Frequency (Connects as phout[7:0] to the ext_phout[7:0] ports of LVDS SERDES IP) |
---|---|---|---|
Frequency | data rate |
data rate/16 |
data rate |
Phase shift | 180° |
180°/16 = 11.25 |
— |
Duty cycle | 50% |
50% |
— |