Agilex™ 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 7/23/2024
Public
Document Table of Contents

5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings

The number of pin settings available depends on the Number of RX channels and Number of TX channels you specify in the General Settings tab.

Each byte and pin pair combination must be unique in the LVDS SERDES interface across receivers and transmitters. The combination of the channel byte and pins, and which I/O lane you place the channel byte, determines the pins locations within the I/O bank.

If you want to customize the pin selections, Altera recommends that you first plan your LVDS SERDES interface channels placement before configuring the Pin Settings tab. Refer to the related information.

Table 13.  Pin Settings Tab—Customize Pin Selection
Parameter Value Description
Customize Pin Selections
  • On
  • Off
  • Turn on to manually select each byte and pin pair reference for the RX and TX channels.
  • Turn off to automatically specify all byte and pin pair references.
    • Use the Quartus® Prime Interface Planner tool to place each byte in an I/O lane.
    • Refer to the related information for:
      • The equivalent pin index numbers based on which I/O lane you place each channel.
      • The differential pin placement restrictions.

Default is Off.

Table 14.  Pin Settings Tab—RX Pin Settings
Parameter Value Description
RX channel n byte 00 to 07

Select the byte reference to use for the RX channel.

Use the Quartus® Prime Interface Planner tool to place the byte in an I/O lane. Refer to the related information for differential pin placement restrictions.

RX channel n pin
  • 0001
  • 0203
  • 0405
  • 0607
  • 0809
  • 1011

Select the pin pair reference within the byte.

Refer to the related information for which pin pair to select based on which pin index numbers and I/O lane you want to place the channel.

Table 15.  Pin Settings Tab—TX Pin Settings
Parameter Value Description
TX outclock channel byte 00 to 07

Select the byte reference to use for the TX outclock.

Use the Quartus® Prime Interface Planner tool to place the byte in an I/O lane. Refer to the related information for differential pin placement restrictions.

TX outclock channel pin
  • 0001
  • 0203
  • 0405
  • 0607
  • 0809
  • 1011

Select the TX outclock pin pair reference within the byte.

Refer to the related information for which pin pair to select based on which pin index numbers and I/O lane you want to place the TX outclock.

TX channel n byte 00 to 07

Select the byte reference to use for the TX channel.

Use the Quartus® Prime Interface Planner tool to place the byte in an I/O lane. Refer to the related information for differential pin placement restrictions.

TX channel n pin
  • 0001
  • 0203
  • 0405
  • 0607
  • 0809
  • 1011

Select the pin pair reference within the byte.

Refer to the related information for which pin pair to select based on which pin index numbers and I/O lane you want to place the channel.