Agilex™ 7 LVDS SERDES User Guide: M-Series

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ID 768615
Date 7/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 M-Series LVDS SERDES Overview 2. Agilex™ 7 M-Series LVDS SERDES Architecture 3. Agilex™ 7 M-Series LVDS SERDES Transmitter 4. Agilex™ 7 M-Series LVDS SERDES Receiver 5. Agilex™ 7 M-Series High-Speed LVDS I/O Implementation Guide 6. Agilex™ 7 M-Series LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Agilex™ 7 M-Series LVDS SERDES Design Guidelines 9. Agilex™ 7 M-Series LVDS SERDES Troubleshooting Guidelines 10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: M-Series 11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: M-Series
1. Agilex™ 7 M-Series LVDS SERDES Overview x
1.1. LVDS SERDES Usage Modes
2. Agilex™ 7 M-Series LVDS SERDES Architecture x
2.1. Agilex™ 7 M-Series GPIO-B Banks, SERDES, and DPA Locations 2.2. SERDES Blocks, Modes, and Clock Domains
3. Agilex™ 7 M-Series LVDS SERDES Transmitter x
3.1. LVDS SERDES Transmitter Blocks 3.2. Serializer 3.3. Clocking the Differential Transmitters
3.2. Serializer x
3.2.1. Serializer Bypass for DDR and SDR Operations 3.2.2. Differential I/O Bit Position
3.3. Clocking the Differential Transmitters x
3.3.1. Transmitter Output Clock Parameters Settings
3.3.1. Transmitter Output Clock Parameters Settings x
3.3.1.1. Edge-Aligned tx_outclock to tx_out
4. Agilex™ 7 M-Series LVDS SERDES Receiver x
4.1. LVDS SERDES Receiver Blocks 4.2. Clocking the LVDS SERDES Receivers 4.3. LVDS SERDES Receiver Modes
4.1. LVDS SERDES Receiver Blocks x
4.1.1. Dynamic Phase Alignment Block 4.1.2. Synchronizer (DPA FIFO) 4.1.3. Data Realignment Block (Bit Slip) 4.1.4. Deserializer
4.2. Clocking the LVDS SERDES Receivers x
4.2.1. Receiver Input Clock Parameters Settings
4.2.1. Receiver Input Clock Parameters Settings x
4.2.1.1. Edge-Aligned inclock to rx_in 4.2.1.2. Center-Aligned inclock to rx_in
4.3. LVDS SERDES Receiver Modes x
4.3.1. Non-DPA Mode 4.3.2. DPA Mode 4.3.3. Soft-CDR Mode
5. Agilex™ 7 M-Series High-Speed LVDS I/O Implementation Guide x
5.1. LVDS SERDES Intel® FPGA IP 5.2. LVDS Interface with External PLL Mode 5.3. LVDS SERDES IP Initialization and Reset
5.1. LVDS SERDES Intel® FPGA IP x
5.1.1. Release Information 5.1.2. LVDS SERDES Intel® FPGA IP Features 5.1.3. LVDS SERDES IP Usage Modes 5.1.4. Planning the LVDS SERDES Interface 5.1.5. Generating the LVDS SERDES Intel® FPGA IP 5.1.6. LVDS SERDES Intel® FPGA IP Parameter Settings 5.1.7. LVDS SERDES Intel® FPGA IP Signals
5.1.5. Generating the LVDS SERDES Intel® FPGA IP x
5.1.5.1. Intel® FPGA IP Generation Output
5.1.6. LVDS SERDES Intel® FPGA IP Parameter Settings x
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings 5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings 5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings 5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings 5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings 5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings x
5.1.6.2.1. GPIO-B Pin Index Number and Respective Channel Pin Selection 5.1.6.2.2. Placing Channel Bytes in I/O Lanes 5.1.6.2.3. Locating the I/O Lane and Channel Pin through the Interface Planner
5.2. LVDS Interface with External PLL Mode x
5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP 5.2.2. IOPLL Parameter Values for External PLL Mode 5.2.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
5.3. LVDS SERDES IP Initialization and Reset x
5.3.1. Initializing the LVDS SERDES IP in Non-DPA Mode 5.3.2. Initializing the LVDS SERDES IP in DPA Mode 5.3.3. Resetting the DPA 5.3.4. Word Boundaries Alignment
5.3.4. Word Boundaries Alignment x
5.3.4.1. Aligning Word Boundaries
6. Agilex™ 7 M-Series LVDS SERDES Timing x
6.1. LVDS SERDES Intel® FPGA IP Timing 6.2. LVDS SERDES Source-Synchronous Timing Budget
6.1. LVDS SERDES Intel® FPGA IP Timing x
6.1.1. I/O Timing Analysis 6.1.2. FPGA Timing Analysis 6.1.3. Timing Analysis for the External PLL Mode
6.1.1. I/O Timing Analysis x
6.1.1.1. Obtaining RSKM Report 6.1.1.2. Obtaining TCCS Report
6.2. LVDS SERDES Source-Synchronous Timing Budget x
6.2.1. Transmitter Channel-to-Channel Skew 6.2.2. Receiver Skew Margin
7. LVDS SERDES Intel® FPGA IP Design Examples x
7.1. LVDS SERDES IP Synthesizable Quartus® Prime Design Examples 7.2. LVDS SERDES IP Simulation Design Example
8. Agilex™ 7 M-Series LVDS SERDES Design Guidelines x
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES 8.2. Use High-Speed Clock from PLL to Clock SERDES Only 8.3. Pin Placement for Differential Channels 8.4. SERDES Pin Pairs for Soft-CDR Mode 8.5. Placing LVDS SERDES Transmitters and Receivers in the Same GPIO-B Sub-Bank with External PLL 8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs 8.7. VCCIO_PIO Power Scheme for LVDS SERDES
8.3. Pin Placement for Differential Channels x
8.3.1. I/O PLLs Driving LVDS SERDES Transmitter and Receiver Channels 8.3.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank
1. Agilex™ 7 M-Series LVDS SERDES Overview
2. Agilex™ 7 M-Series LVDS SERDES Architecture
3. Agilex™ 7 M-Series LVDS SERDES Transmitter
4. Agilex™ 7 M-Series LVDS SERDES Receiver
5. Agilex™ 7 M-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 M-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 M-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 M-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: M-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: M-Series

5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings

The number of pin settings available depends on the Number of RX channels and Number of TX channels you specify in the General Settings tab.

Each byte and pin pair combination must be unique in the LVDS SERDES interface across receivers and transmitters. The combination of the channel byte and pins, and which I/O lane you place the channel byte, determines the pins locations within the I/O bank.

If you want to customize the pin selections, Altera recommends that you first plan your LVDS SERDES interface channels placement before configuring the Pin Settings tab. Refer to the related information.

Table 13.  Pin Settings Tab—Customize Pin Selection
Parameter Value Description
Customize Pin Selections
  • On
  • Off
  • Turn on to manually select each byte and pin pair reference for the RX and TX channels.
  • Turn off to automatically specify all byte and pin pair references.
    • Use the Quartus® Prime Interface Planner tool to place each byte in an I/O lane.
    • Refer to the related information for:
      • The equivalent pin index numbers based on which I/O lane you place each channel.
      • The differential pin placement restrictions.

Default is Off.
Table 14.  Pin Settings Tab—RX Pin Settings
Parameter Value Description
RX channel n byte 00 to 07

Select the byte reference to use for the RX channel.

Use the Quartus® Prime Interface Planner tool to place the byte in an I/O lane. Refer to the related information for differential pin placement restrictions.

RX channel n pin
  • 0001
  • 0203
  • 0405
  • 0607
  • 0809
  • 1011

Select the pin pair reference within the byte.

Refer to the related information for which pin pair to select based on which pin index numbers and I/O lane you want to place the channel.

Table 15.  Pin Settings Tab—TX Pin Settings
Parameter Value Description
TX outclock channel byte 00 to 07

Select the byte reference to use for the TX outclock.

Use the Quartus® Prime Interface Planner tool to place the byte in an I/O lane. Refer to the related information for differential pin placement restrictions.

TX outclock channel pin
  • 0001
  • 0203
  • 0405
  • 0607
  • 0809
  • 1011

Select the TX outclock pin pair reference within the byte.

Refer to the related information for which pin pair to select based on which pin index numbers and I/O lane you want to place the TX outclock.

TX channel n byte 00 to 07

Select the byte reference to use for the TX channel.

Use the Quartus® Prime Interface Planner tool to place the byte in an I/O lane. Refer to the related information for differential pin placement restrictions.

TX channel n pin
  • 0001
  • 0203
  • 0405
  • 0607
  • 0809
  • 1011

Select the pin pair reference within the byte.

Refer to the related information for which pin pair to select based on which pin index numbers and I/O lane you want to place the channel.


Section Content
GPIO-B Pin Index Number and Respective Channel Pin Selection
Placing Channel Bytes in I/O Lanes
Locating the I/O Lane and Channel Pin through the Interface Planner

Related Information
Level Two Title