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1. Agilex™ 7 M-Series LVDS SERDES Overview
2. Agilex™ 7 M-Series LVDS SERDES Architecture
3. Agilex™ 7 M-Series LVDS SERDES Transmitter
4. Agilex™ 7 M-Series LVDS SERDES Receiver
5. Agilex™ 7 M-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 M-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 M-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 M-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: M-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: M-Series
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers in the Same GPIO-B Sub-Bank with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
8.7. VCCIO_PIO Power Scheme for LVDS SERDES
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5.1.5. Generating the LVDS SERDES Intel® FPGA IP
Using the LVDS SERDES Intel® FPGA IP parameter editor, you can customize the IP settings and generate the IP variant files, simulation testbench, and HDL instantiation template.
Before you begin, create or open a Quartus® Prime project. You should also plan your LVDS SERDES interface pin placements. Refer to the related information.
Figure 21. LVDS SERDES Intel FPGA IP Parameter Editor
- In the IP Catalog window, double-click LVDS SERDES Intel® FPGA IP .
The Parameter Editor window appears.
- Specify a top-level name for your new IP variant and click Create.
Do not include space and special characters in the name and file path.
- Set the values in the General Settings, Pin Settings, PLL Settings, Receiver Settings, and Transmitter Settings tabs.
- Setting up the Pin Settings tab requires you to plan your LVDS SERDES interface in advance. Refer to the related information.
- The System Messages tab displays errors and warning for the parameters settings. Refer to the related information for the valid parameter values.
- From the Parameter Editor menu, select File > Save.
The parameter editor saves the IP variant settings in the <your_ip> .ip file.
- To generate the IP variant HDL files:
- Click Generate HDL.
The Generation window appears.
- Specify the output file generation options and click Generate.
The parameter editor generates the synthesis and simulation files as you specified, and automatically adds the .ip file of the variant to your project.
- Click Close.
- Click Generate HDL.
- To generate a simulation testbench:
- From the Parameter Editor menu, select Generate > Generate Testbench System.
- Specify the testbench generation options and click Generate.
- Click Close.
- To generate an HDL instantiation template that you can copy and paste into your text editor:
- From the Parameter Editor menu, select Generate > Show Instantiation Template.
- Select the HDL Language.
The code template appears in the Example HDL box.
- Click Copy and then click Close.
After generating and instantiating your IP variant, assign appropriate pins to connect the ports.