Agilex™ 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 7/23/2024
Public
Document Table of Contents

3. Agilex™ 7 M-Series LVDS SERDES Transmitter

The M-Series LVDS SERDES transmitters are dedicated circuitries.

Each dedicated transmitter circuitry consists of:

  • A transmitter buffer
  • A serializer
  • PLL shared with other SERDES within the same I/O bank
Table 4.  Dedicated Circuitry and Features of the LVDS SERDES Transmitter
Dedicated Circuitry / Feature Description
Differential I/O buffer Supports True Differential Signaling I/O standard, which is compatible with LVDS, RSDS, SLVS, and Mini-LVDS.
Serializer 3 4-bit or 8-bit4 wide serializer
Phase-locked loops (PLLs) Clocks the registers
Programmable VOD Adjusts the output voltage swing
Programmable pre-emphasis Boosts output current
3 Serialization factors of 1 and 2 are supported through the GPIO Intel® FPGA IP.
4 Serialization factor of 8 is available only in M-Series FPGAs production devices.