Agilex™ 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 7/23/2024
Public
Document Table of Contents

5.1.6.2.1. GPIO-B Pin Index Number and Respective Channel Pin Selection

The channel byte is a reference number to assign to an I/O lane. The placement of the pin pair on the I/O bank depends on which I/O lane you place the specific channel byte. If you turn on Customize Pin Selections, select the channel pin in the Pin Settings tab based on the pin index number within the GPIO-B bank. If you turn off Customize Pin Selections, use the table to identify which pin index pair the LVDS SERDES IP uses.
Table 16.  Channel Pin in the Pin Settings Tab for Each GPIO-B Bank Pin Index Number Pair
Pin Index Pair within GPIO-B Bank Channel Pin
Bottom Index Sub-Bank Top Index Sub-Bank
Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7
0/1 12/13 24/25 36/37 48/49 60/61 72/73 84/85 0001
2/3 14/15 26/27 38/39 50/51 62/63 74/75 86/87 0203
4/5 16/17 28/29 40/41 52/53 64/65 76/77 88/89 0405
6/7 18/19 30/31 42/43 54/55 66/67 78/79 90/91 0607
8/9 20/21 32/33 44/45 56/57 68/69 80/81 92/93 0809
10/11 22/23 34/35 46/47 58/59 70/71 82/83 94/95 1011

For example, the RX channel 0 byte selection is 01 and the RX channel 0 pin selection is 0203. If you place byte 01 in lane 3 of the GPIO-B bank, the channel 0 location is pins with index numbers 38 and 39 within the bottom index sub-bank.

Figure 23. Pin Settings Tab Example