Agilex™ 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 7/23/2024
Public
Document Table of Contents

3.2. Serializer

The serializer consists of two sets of registers. The first set of registers (FIFO) captures the parallel data from the core using the LVDS fast clock and then transfers the data to the serializer block. The MSB of the serializer feeds the LVDS SERDES output buffer. Consequently, higher order bits precede lower order bits in the output bitstream.
Figure 4. LVDS SERDES ×8 Serializer Bit PositionThis figure shows the waveforms specific to the serialization factor of 8. These are functional waveforms and do not convey timing information.


Table 5.  LVDS SERDES Serializer Signals
Signal Description
tx_in[7:0]

Data for serialization

(Supported serialization factors: 4 and 85 )

fast_clock

Clock for the transmitter

tx_out LVDS SERDES output data stream
5 Serialization factor of 8 is available only in M-Series FPGAs production devices.