Agilex™ 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 7/23/2024
Public
Document Table of Contents

8.3.1. I/O PLLs Driving LVDS SERDES Transmitter and Receiver Channels

The following figures show valid and invalid scenarios of the GPIO-B bank PLLs driving the transmitter and receiver channels.
Figure 37. I/O PLL Driving Transmitter or Receiver Channels in the Same Sub-BankThe I/O PLL can drive the transmitter or receiver channels in its own sub-bank.


Figure 38. I/O PLL Driving Mixed Receiver and Transmitter Channels in the Same Sub-BankThe I/O PLL can drive transmitter and receiver channels in the same sub-bank if the channels have identical data rates. If the transmitter and receiver channels have different data rates, you need another PLL.


Figure 39. I/O PLL Driving Transmitter or Receiver Channels Across Sub-BanksThe I/O PLL can drive channels across sub-banks if the channels have identical data rates.


Figure 40. I/O PLL Driving Transmitter or Receiver Channels in Another Sub-BankThe I/O PLL can drive channels in another sub-bank. In this valid scenario, you may have to use a reference clock tree. However, the I/O PLL cannot drive channels in different sub-banks with different data rates.