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1. Agilex™ 7 M-Series LVDS SERDES Overview
2. Agilex™ 7 M-Series LVDS SERDES Architecture
3. Agilex™ 7 M-Series LVDS SERDES Transmitter
4. Agilex™ 7 M-Series LVDS SERDES Receiver
5. Agilex™ 7 M-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 M-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 M-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 M-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: M-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: M-Series
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers in the Same GPIO-B Sub-Bank with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
8.7. VCCIO_PIO Power Scheme for LVDS SERDES
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5.1.3. LVDS SERDES IP Usage Modes
You can implement four usage modes using the LVDS SERDES IP.
- Transmitter—specify the Number of TX channels to generate the IP as a transmitter.
- Non-DPA receiver—specify the Number of RX channels and select the RX Non-DPA option to generate the IP as non-DPA receiver.
- DPA receiver—specify the Number of RX channels and select the RX DPA-FIFO option to generate the IP as DPA receiver.
- Soft CDR receiver—specify the Number of RX channels and select the RX Soft-CDR option to generate the IP as soft-CDR receiver.
Each GPIO-B sub-bank can support one IP instance with a maximum of 12 transmitter and 12 receiver channels. For designs with more than 12 channels, you must generate a new LVDS SERDES IP instance and place it in a new GPIO-B sub-bank.
Number of Channels | Usage Modes | PLL Configuration | Number of IP Instances | |
---|---|---|---|---|
1–47 Maximum of 24 transmitter and receiver channels combination per sub-bank. |
Transmitters and receivers |
|
2 |
|
1–23 | Transmitters | External PLL | 1 | |
Internal PLL | 1 | |||
1–23 | Receivers | External PLL | 1 | |
Internal PLL | 1 |
Note: You must use one of the differential pin pairs for the I/O PLL reference clock.