Agilex™ 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 7/23/2024
Public
Document Table of Contents

5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings

The parameter options in the Receiver Settings tab are available if you select the RX Non-DPA, RX DPA-FIFO, or RX Soft-CDR functional mode in the General Settings tab.
Table 18.  Receiver Settings Tab—Bitslip Settings
Parameter Value Description
Enable bitslip mode
  • On
  • Off

Turn on to add a bit slip block to the receiver data path and expose the rx_bitslip_ctrl port (one input per channel).

Every assertion of the rx_bitslip_ctrl signal adds one bit of serial latency to the data path of the specified channel.

Enable rx_bitslip_reset port
  • On
  • Off

Turn on to expose the rx_bitslip_reset port (one input per channel) that you can use to reset the bit slip.

Enable rx_bitslip_max port
  • On
  • Off

Turn on to expose the rx_bitslip_max port (one output per channel).

When asserted, the next rising edge of rx_bitslip_ctrl resets the latency of the bit slip to zero.

Table 19.  Receiver Settings Tab—DPA Settings
Parameter Value Description
Enable rx_dpa_reset port
  • On
  • Off

Turn on to expose the rx_dpa_reset port that you can use to reset the DPA logic of each channel independently.

(Formerly known as rx_reset.)

Enable rx_fifo_reset port
  • On
  • Off

Turn on to use your logic to drive the rx_fifo_reset port to reset the DPA-FIFO block.

Enable rx_dpa_hold port
  • On
  • Off

Turn on to expose the rx_dpa_hold input port (one input per channel).

If set high, the DPA logic in the corresponding channel does not switch sampling phases.

(Formerly known as rx_dpll_hold.)

Table 20.  Receiver Settings Tab—Non-DPA Settings
Parameter Value Description
Desired receiver inclock phase shift (degrees)

Specifies, in degrees of the LVDS fast clock, the ideal phase delay of inclock with respect to transitions in the incoming serial data.

For example, specifying 180° implies that the inclock is center aligned to the incoming data.

Actual receiver inclock phase shift (degrees)

Depends on the fast_clock and inclock frequencies. Refer to the related information.

Specifies the closest achievable receiver inclock phase shift to the desired receiver inclock phase shift.