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1. Agilex™ 7 M-Series LVDS SERDES Overview
2. Agilex™ 7 M-Series LVDS SERDES Architecture
3. Agilex™ 7 M-Series LVDS SERDES Transmitter
4. Agilex™ 7 M-Series LVDS SERDES Receiver
5. Agilex™ 7 M-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 M-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 M-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 M-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: M-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: M-Series
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers in the Same GPIO-B Sub-Bank with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
8.7. VCCIO_PIO Power Scheme for LVDS SERDES
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1.1. LVDS SERDES Usage Modes
You can use the M-Series LVDS SERDES through the LVDS SERDES Intel® FPGA IP. The LVDS SERDES IP supports four SERDES functional modes.
Functional Mode | Description |
---|---|
Transmitter (TX) |
|
Non-DPA receiver (RX Non-DPA) |
|
DPA-FIFO receiver (RX DPA-FIFO) |
|
Soft-CDR receiver (RX Soft-CDR) |
|
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