Visible to Intel only — GUID: gmq1658805441227
Ixiasoft
1. Agilex™ 7 M-Series LVDS SERDES Overview
2. Agilex™ 7 M-Series LVDS SERDES Architecture
3. Agilex™ 7 M-Series LVDS SERDES Transmitter
4. Agilex™ 7 M-Series LVDS SERDES Receiver
5. Agilex™ 7 M-Series High-Speed LVDS I/O Implementation Guide
6. Agilex™ 7 M-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 7 M-Series LVDS SERDES Design Guidelines
9. Agilex™ 7 M-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Agilex™ 7 LVDS SERDES User Guide: M-Series
11. Document Revision History for the Agilex™ 7 LVDS SERDES User Guide: M-Series
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers in the Same GPIO-B Sub-Bank with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
8.7. VCCIO_PIO Power Scheme for LVDS SERDES
Visible to Intel only — GUID: gmq1658805441227
Ixiasoft
1. Agilex™ 7 M-Series LVDS SERDES Overview
Updated for: |
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Intel® Quartus® Prime Design Suite 24.2 |
The Agilex™ 7 M-Series I/O system includes three types of I/O interfaces: general purpose I/Os (GPIO-B), Secure Device Manager (SDM) I/O, and Hard Processor System (HPS) I/O. Each I/O interface caters to different interfacing requirements.
M-Series devices support LVDS serializer/deserializer (SERDES) through True Differential Signaling and SLVS-400 I/O standards in the GPIO-B banks. The true differential I/Os are capable of supporting LVDS interfaces, including subsets such as:
- RSDS
- Mini-LVDS
- SLVS
- Any differential I/O standards using equivalent electrical specifications
M-Series devices support SERDES in all GPIO-B banks with the following features:
- Configurable transmitter or receiver on all I/O pins
- Serialize and deserialize functions up to 1.6 Gbps.
- Clock data recovery (CDR) function on specific differential channel
- Configurable 100 Ω differential on-chip termination (OCT RD)
- Serializer or deserializer factors of 4 and 81
- I/O standards support for the LVDS SERDES:
- Transmitter—True Differential Signaling I/O standard at 1.3 V
- Receiver:
- DPA mode—True Differential Signaling and SLVS-400 I/O standards
- Non-DPA mode—True Differential Signaling I/O standard only
1 Serialization factor of 8 is available only in M-Series FPGAs production devices.