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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP User Guide Archives
9. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
6.1. Clock and Reset Signals
6.2. Speed Selection Signal
6.3. Error Correction Signals
6.4. Avalon® Memory-Mapped Interface Programming Signals
6.5. Avalon® Streaming Data Interfaces
6.6. Avalon® Streaming Flow Control Signals
6.7. Avalon® Streaming Status Interface
6.8. PHY-side Interfaces
6.9. IEEE 1588v2 Interfaces
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7.9.1. Calculating PHY Total Latency
The IEEE 1588 feature enables the 1G/2.5G/5G/10G Multirate Ethernet PHY IP core to provide the datapath latency measurements to the MAC. The total latency of the PHY IP core is the total sum of the PCS and PMA datapath latency.
Datapath Latency | Description |
---|---|
PCS | The xgmii_tx_latency and xgmii_rx_latency output ports to Low Latency Ethernet 10G MAC. The PCS latency is derived from the Deterministic Latency (DL) calculation of the Multi-rate Ethernet PHY IP. Refer to Calculating Deterministic Latency. |
PMA | The PMA latency is provided in the F-Tile Ethernet Hard IP User Guide. Refer to PMA Delay of 10.3125 Gbps FGT PMA Rate. The sum of PCS and PMA delay is written to TX and RX static timing adjustment registers. |
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