F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 720985
Date 4/18/2024
Public
Document Table of Contents

7.9.1. Calculating PHY Total Latency

The IEEE 1588 feature enables the 1G/2.5G/5G/10G Multirate Ethernet PHY IP core to provide the datapath latency measurements to the MAC. The total latency of the PHY IP core is the total sum of the PCS and PMA datapath latency.
Table 42.  Total Datapath Latency Components
Datapath Latency Description
PCS

The xgmii_tx_latency and xgmii_rx_latency output ports to Low Latency Ethernet 10G MAC.

The PCS latency is derived from the Deterministic Latency (DL) calculation of the Multi-rate Ethernet PHY IP. Refer to Calculating Deterministic Latency.

PMA

The PMA latency is provided in the F-Tile Ethernet Hard IP User Guide. Refer to PMA Delay of 10.3125 Gbps FGT PMA Rate.

The sum of PCS and PMA delay is written to TX and RX static timing adjustment registers.