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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP User Guide Archives
9. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
6.1. Clock and Reset Signals
6.2. Speed Selection Signal
6.3. Error Correction Signals
6.4. Avalon® Memory-Mapped Interface Programming Signals
6.5. Avalon® Streaming Data Interfaces
6.6. Avalon® Streaming Flow Control Signals
6.7. Avalon® Streaming Status Interface
6.8. PHY-side Interfaces
6.9. IEEE 1588v2 Interfaces
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2.5.1. Resource Utilization
The estimated resource utilization for all operating modes are obtained by compiling the Low Latency Ethernet 10G MAC Intel® FPGA IP core with the Quartus® Prime software targeting on Agilex™ 7 (F-Tile) devices. These estimates are generated by the fitter, excluding the virtual I/Os.
MAC Settings | ALMs | ALUTs | Logic Registers | Memory Block (M20K) | |||
---|---|---|---|---|---|---|---|
Operating Mode | Enabled Options | ||||||
10M/100M/1G/2.5G/5G/10G (USXGMII) | Supplementary addresses. Memory-based statistics counters. |
3,320 | 4,558 | 6,170 | 10 | ||
Supplementary addresses. Memory-based statistics counters. Timestamping. |
5,428 | 7,649 | 11,003 | 35 |