F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 720985
Date 4/18/2024
Public
Document Table of Contents

6.1. Clock and Reset Signals

The Low Latency Ethernet 10G MAC Intel® FPGA IP core operates in multiple clock domains. You can use different sources to drive the clock and reset domains. You can also use the same clock source as specified in the description of each signal.

Table 18.  Clock and Reset SignalsThis table lists the supported clock and reset signals for the 10M/100M/1G/2.5G/5G/10G (USXGMII) operating mode.
Signal Direction Width Description
tx_312_5_clk In 1 312.5 MHz clock for the MAC TX datapath. You may use the same clock source for this clock with rx_312_5_clk.
tx_156_25_clk In 1

156.25 MHz clock for the MAC TX datapath when you choose to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® streaming TX data interface.

Intel recommends that this clock and tx_312_5_clk share the same clock source. This clock must be synchronous to tx_312_5_clk. Their rising edges must align and must have 0 ppm and phase-shift.

rx_312_5_clk In 1 312.5 MHz clock for the MAC RX datapath. You may use the same clock source for this clock with tx_312_5_clk.
rx_156_25_clk In 1

156.25MHz clock for the MAC RX datapath when you choose to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® streaming RX data interface.

Intel recommends that you use the same clock source for this clock and rx_312_5_clk. This clock must be synchronous to rx_312_5_clk. Their rising edges must align and must have 0 ppm and phase-shift.

csr_clk In 1 100 MHz -156.25 MHz clock for the CSR read and write registers .
tx_rst_n In 1 Active-low asynchronous reset in the tx_312_5_clk clock domain for the MAC TX datapath
rx_rst_n In 1

Active-low reset in the rx_312_5_clk clock domain for the MAC RX datapath.

csr_rst_n In 1

Active-low reset in the csr_clk clock domain for the CSR registers.