Visible to Intel only — GUID: bhc1395127713616
Ixiasoft
Visible to Intel only — GUID: bhc1395127713616
Ixiasoft
4.6.1.2. Pause Frame Transmission
Use one of the following methods to trigger pause frame transmission:
- avalon_st_pause_data signal (tx_pauseframe_enable[2:1] set to 0)—You can connect this 2-bit signal to a FIFO buffer or a client. Bit setting:
- avalon_st_pause_data[1]: 1—triggers the transmission of XOFF pause frames.
- avalon_st_pause_data[0]: 1—triggers the transmission of XON pause frames. The transmission of XON pause frames only trigger for one time after XOFF pause frames regardless of how long the avalon_st_pause_data[0] signal is asserted.
- tx_pauseframe_control register (tx_pauseframe_enable[2:0] set to 0x1)—A host (software) can set this register to trigger pause frames transmission. Setting tx_pauseframe_control[1] to 1 triggers the transmission of XOFF pause frames; setting tx_pauseframe_control[0] to 1 triggers the transmission of XON pause frames. The register clears itself after the request is executed.
You can configure the pause quanta in the tx_pauseframe_quanta register. The MAC sets the pause quanta field in XOFF pause frames to this register value.
The following figure shows the transmission of an XON pause frame. The MAC sets the destination address field to the global multicast address, 01-80-C2-00-00-01 (0x010000c28001) and the source address to the MAC primary address configured in the tx_addrins_macaddr0 and tx_addrins_madaddr1 registers.