Visible to Intel only — GUID: mca1652928250541
Ixiasoft
Visible to Intel only — GUID: mca1652928250541
Ixiasoft
7.9.2. Calculating Deterministic Latency
Item | Value | Description |
---|---|---|
sampling_clk_period | 6.5ns |
Period for sampling clock (latency_sclk) of 153.846 MHz |
UI period | 0.0969696..ns |
Period for unit interval |
bitslip_cnt | Read from pcs_bitslip_cnt[6:0] | Read from the Ethernet Reconfiguration Interface register (pcs_bitslip_cnt) at base 0x1000, register offset 0x110. |
dlpulse_alignment | Read from pcs_bitslip_cnt[7] | Read from the Ethernet Reconfiguration Interface register (pcs_bitslip_cnt) at base 0x1000, register offset 0x110. |
tx_delay (TxDL) | Read from PTP_DL_TX register 0x421[20:0] |
TX delay value in sampling_clk cycles, fixed point format Q13.8. Bit [20:8] is integer, bit [7:0] is fractional. Example: tx_delay = 0x27F4, Bit [20:8] = 0x27 = 39, Bit [7:0] = 0xF4 = 244/2^8 = 0.953125, Hence, tx_delay = 39.953125 clock cycles. |
rx_delay (RxDL) | Read from PTP_DL_RX register 0x422[20:0] |
RX delay value in sampling_clk cycles, fixed point format Q13.8. Bit [20:8] is integer, bit [7:0] is fractional. |
TX PMA Delay | Simulation: 80 Hardware: 79 |
TX PMA delay in the number of UI. Multiply by UI period to convert to nanoseconds and fractional nanoseconds format. |
RX PMA Delay | Simulation: 88 Hardware: 88 |
RX PMA delay in the number of UI. Multiply by UI period to convert to nanoseconds and fractional nanoseconds format. |
TX Latency = TxDL * (sampling_clock_period in ns)
RX Latency = RxDL * (sampling_clock_period in ns) + (- bitslip_cnt - 33 * dlpulse_alignment) * (UI period in ns)