F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 720985
Date 4/18/2024
Public
Document Table of Contents

5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters

You customize the Intel® FPGA IP core by specifying the parameters on the parameter editor in the Quartus® Prime software. The parameter editor enables only the parameters that are applicable to the selected speed.

Table 17.   Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
Parameter Value Description
MAC Options
Speed 10M/100M/1G/2.5G/5G/10G (USXGMII) Show the supported speed mode.
Datapath options TX & RX Show the datapath of MAC instance.
  • TX & RX—instantiates both MAC TX and RX.
Enable ECC on memory blocks On, Off Turn on this option to enable error detection and correction on memory blocks.
Enable supplementary address On, Off Turn on this option to enable supplementary addresses. You must also set the EN_SUPP0/1/2/3 bits in the rx_frame_control register to 1.
Enable statistics collection On, Off Turn on this option to collect statistics on the TX and RX datapaths.
Statistics counters Memory-based, Register-based Specify the implementation of the statistics counters. When you turn on Statistics collection, the default implementation of the counters is Memory-based.
  • Memory-based—selecting this option frees up logic elements. The MAC IP core does not clear memory-based counters after they are read.
  • Register-based—selecting this option frees up the memory. The MAC IP core clears register-based statistic counters after the counters are read.

Memory-based statistics counters may not be accurate when the MAC IP core receives or transmits back-to-back undersized frames. On the TX datapath, you can enable padding to avoid this situation. Undersized frames are frames with less than 64 bytes.

TX and RX datapath Reset/Default to Enable On, Off Turn off this option to disable TX and RX datapath during startup or CSR reset.
Timestamp Options
Enable time stamping On, Off Turn on this option to enable time stamping on the TX and RX datapaths.
Enable PTP one-step clock support On, Off Turn on this option to enable 1-step time stamping. This option is enabled only when you turn on time stamping.
Enable asymmetry support On, Off Turn on this option to enable asymmetry support on TX datapath. This option is enabled only when you turn on time stamping and PTP one-step clock support.
Enable peer-to-peer support On, Off Turn on this option to enable peer-to-peer support on TX datapath. This option is enabled only when you turn on time stamping and PTP one-step clock support.
Timestamp fingerprint width 1–32 Specify the width of the timestamp fingerprint in bits on the TX path. The default value is 4 bits.
Time of Day Format Enable 96b Time of Day Format only, Enable 64b Time of Day Format only, Enable both 96b and 64b Time of Day Format Specify the time-of-day format.
Legacy Ethernet 10G MAC Interfaces
Use legacy Ethernet 10G MAC Avalon® memory-mapped interface On, Off Turn on this option to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® memory-mapped interface.
Use legacy Ethernet 10G MAC Avalon® streaming interface On, Off Turn on this option to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® streaming interface.