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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP User Guide Archives
9. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
6.1. Clock and Reset Signals
6.2. Speed Selection Signal
6.3. Error Correction Signals
6.4. Avalon® Memory-Mapped Interface Programming Signals
6.5. Avalon® Streaming Data Interfaces
6.6. Avalon® Streaming Flow Control Signals
6.7. Avalon® Streaming Status Interface
6.8. PHY-side Interfaces
6.9. IEEE 1588v2 Interfaces
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4.10. IEEE 1588v2
The IEEE 1588v2 option provides time stamp for receive and transmit frames in the LL Ethernet 10G MAC IP core designs. The feature consists of Precision Time Protocol (PTP). PTP is a protocol that accurately synchronizes all real time-of-day clocks in a network to a master clock.
The IEEE 1588v2 option has the following features:
- Supports 4 types of PTP clock on the transmit datapath:
- Master and slave ordinary clock
- Master and slave boundary clock
- End-to-end (E2E) transparent clock
- Peer-to-peer (P2P) transparent clock
- Supports PTP with the following message types:
- PTP event messages—Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp.
- PTP general messages—Follow_Up, Delay_Resp, Pdelay_Resp_Follow_Up, Announce, Management, and Signaling.
- Supports simultaneous 1-step and 2-step clock synchronizations on the transmit datapath.
- 1-step clock synchronization—The MAC function inserts accurate timestamp in Sync PTP message or updates the correction field with residence time.
- 2-step clock synchronization—The MAC function provides accurate timestamp and the related fingerprint for all PTP message.
- Supports the following IEEE 1588 accuracy:
Table 15. IEEE 1588 Supported Accuracy Speed Constant Time Error (Static Error) Dynamic Time Error (Random Error) Total Error 10G ± 3ns ± 2ns ± 5 ns 5G ± 3ns ± 2ns ± 5 ns 2.5G ± 3ns ± 2ns ± 5 ns 1G ± 3ns ± 2ns ± 5 ns 100M ± 3ns ± 5 ns ± 8 ns - Supports IEEE 802.3, UDP/IPv4, and UDP/IPv6 protocol encapsulations for the PTP packets.
- Supports untagged, VLAN tagged, and Stacked VLAN Tagged PTP packets, and any number of MPLS labels. The packet classifier under user control parses the packet (Ethernet packet or MPLS packet) and gives the IP core the required offset, at which either the time-of-day (TOD) or correction factor (CF) update can happen.
- Supports configurable register for timestamp correction on both transmit and receive datapaths.
- Supports TOD clock that provides streams of 64-bit and 96-bit timestamps. The 64-bit timestamp is for transparent clock devices and the 96-bit timestamp is for ordinary clock and boundary clock devices.