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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP User Guide Archives
9. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
6.1. Clock and Reset Signals
6.2. Speed Selection Signal
6.3. Error Correction Signals
6.4. Avalon® Memory-Mapped Interface Programming Signals
6.5. Avalon® Streaming Data Interfaces
6.6. Avalon® Streaming Flow Control Signals
6.7. Avalon® Streaming Status Interface
6.8. PHY-side Interfaces
6.9. IEEE 1588v2 Interfaces
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9. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
Document Version | Quartus® Prime Version | IP Version | Changes |
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2024.04.18 | 23.3 | 22.0.3 | Updated PTP Packet Format over IEEE 802.3 diagram to remove 9600 bytes from the payload field and added a footnote to clarify the maximum payload data size. |
2023.12.26 | 23.3 | 22.0.3 | Updated IP version to v22.0.3. Text edits only; no new technical information. |
2023.05.18 | 22.2 | 20.1.0 |
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2022.12.07 | 22.2 | 20.1.0 | Removed mentions of unidirectional mode:
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2022.06.21 | 22.2 | 20.1.0 | Added PTP support for 10M/100M/1G/2.5G/5G/10G USXGMII variant:
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2022.04.01 | 21.4.1 | 20.0.0 | Initial release. |