F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 720985
Date 4/18/2024
Public
Document Table of Contents

9. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.04.18 23.3 22.0.3 Updated PTP Packet Format over IEEE 802.3 diagram to remove 9600 bytes from the payload field and added a footnote to clarify the maximum payload data size.
2023.12.26 23.3 22.0.3 Updated IP version to v22.0.3. Text edits only; no new technical information.
2023.05.18 22.2 20.1.0
  • Updated the frequency range for csr_clk signal in Clock and Reset Signals topic.
  • Updated the product family name to "Intel Agilex 7."
2022.12.07 22.2 20.1.0 Removed mentions of unidirectional mode:
  • Updated Register Map table.
  • Updated TX Configuration and Status Register table.
2022.06.21 22.2 20.1.0 Added PTP support for 10M/100M/1G/2.5G/5G/10G USXGMII variant:
  • Updated the Resource Utilization topic.
  • Added a new Figure: Interface Signals with PTP.
  • Added a new Topic IEEE 1588v2 Interfaces.
  • Updated the Register Map topic.
  • Added a new Topic: Time Stamp Registers.
  • Added a new Topic: Calculating PHY Total Latency.
  • Added a new Topic: Calculating Deterministic Latency.
  • Added a new Topic: PTP Register Configuration.
2022.04.01 21.4.1 20.0.0 Initial release.