Intel® MAX® 10 FPGA Configuration User Guide

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ID 683865
Date 3/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 FPGA Configuration Overview 2. Intel® MAX® 10 FPGA Configuration Schemes and Features 3. Intel® MAX® 10 FPGA Configuration Design Guidelines 4. Intel® MAX® 10 FPGA Configuration IP Core Implementation Guides 5. Dual Configuration Intel® FPGA IP Core References 6. Unique Chip ID Intel® FPGA IP Core References 7. Document Revision History for the Intel® MAX® 10 FPGA Configuration User Guide
2. Intel® MAX® 10 FPGA Configuration Schemes and Features x
2.1. Configuration Schemes 2.2. Configuration Features 2.3. Configuration Details
2.1. Configuration Schemes x
2.1.1. JTAG Configuration 2.1.2. Internal Configuration
2.1.1. JTAG Configuration x
2.1.1.1. JTAG Pins
2.1.2. Internal Configuration x
2.1.2.1. Internal Configuration Modes 2.1.2.2. Configuration Flash Memory 2.1.2.3. In-System Programming 2.1.2.4. Initialization Configuration Bits 2.1.2.5. Internal Configuration Time
2.1.2.2. Configuration Flash Memory x
2.1.2.2.1. Configuration Flash Memory Sectors 2.1.2.2.2. Configuration Flash Memory Programming Time
2.1.2.3. In-System Programming x
2.1.2.3.1. ISP Clamp 2.1.2.3.2. Real-Time ISP 2.1.2.3.3. ISP and Real-Time ISP Instructions
2.2. Configuration Features x
2.2.1. Remote System Upgrade 2.2.2. Configuration Design Security 2.2.3. SEU Mitigation and Configuration Error Detection 2.2.4. Configuration Data Compression
2.2.1. Remote System Upgrade x
2.2.1.1. Remote System Upgrade Flow 2.2.1.2. Remote System Upgrade Circuitry 2.2.1.3. User Watchdog Timer 2.2.1.4. Dual Configuration Intel® FPGA IP Core
2.2.1.2. Remote System Upgrade Circuitry x
2.2.1.2.1. Remote System Upgrade Circuitry Signals 2.2.1.2.2. Remote System Upgrade Circuitry Input Control 2.2.1.2.3. Remote System Upgrade Input Register 2.2.1.2.4. Remote System Upgrade Status Registers 2.2.1.2.5. Master State Machine
2.2.2. Configuration Design Security x
2.2.2.1. AES Encryption Protection 2.2.2.2. Unique Chip ID 2.2.2.3. JTAG Secure Mode 2.2.2.4. Verify Protect 2.2.2.5. JTAG Instruction Availability 2.2.2.6. Configuration Flash Memory Permissions
2.2.2.1. AES Encryption Protection x
2.2.2.1.1. Encryption and Decryption
2.2.2.2. Unique Chip ID x
2.2.2.2.1. Unique Chip ID Intel® FPGA IP Core
2.2.2.3. JTAG Secure Mode x
2.2.2.3.1. JTAG Secure Mode Instructions
2.2.2.6. Configuration Flash Memory Permissions x
2.2.2.6.1. Flash Region Access Control and Immutability
2.2.3. SEU Mitigation and Configuration Error Detection x
2.2.3.1. Configuration Error Detection 2.2.3.2. User Mode Error Detection 2.2.3.3. Error Detection Timing 2.2.3.4. Recovering from CRC Errors
2.2.3.2. User Mode Error Detection x
2.2.3.2.1. Error Detection Block 2.2.3.2.2. CHANGE_EDREG JTAG Instruction
2.2.3.3. Error Detection Timing x
2.2.3.3.1. Error Detection Frequency 2.2.3.3.2. Cyclic Redundancy Check Calculation Timing
2.3. Configuration Details x
2.3.1. Configuration Sequence 2.3.2. Intel® MAX® 10 Configuration Pins
2.3.1. Configuration Sequence x
2.3.1.1. Power-up 2.3.1.2. Configuration 2.3.1.3. Configuration Error Handling 2.3.1.4. Initialization 2.3.1.5. User Mode
2.3.1.1. Power-up x
2.3.1.1.1. POR Monitored Voltage Rails for Single-supply and Dual-supply Intel® MAX® 10 Devices 2.3.1.1.2. Monitored Power Supplies Ramp Time Requirement for Intel® MAX® 10 Devices
3. Intel® MAX® 10 FPGA Configuration Design Guidelines x
3.1. Dual-Purpose Configuration Pins 3.2. Configuring Intel® MAX® 10 Devices using JTAG Configuration 3.3. Configuring Intel® MAX® 10 Devices using Internal Configuration 3.4. Implementing ISP Clamp in Intel® Quartus® Prime Software 3.5. Accessing Remote System Upgrade through User Logic 3.6. Error Detection 3.7. Enabling Data Compression 3.8. AES Encryption 3.9. Intel® MAX® 10 JTAG Secure Design Example
3.1. Dual-Purpose Configuration Pins x
3.1.1. Guidelines: Dual-Purpose Configuration Pin 3.1.2. Enabling Dual-Purpose Pin
3.1.1. Guidelines: Dual-Purpose Configuration Pin x
3.1.1.1. JTAG Pin Sharing Behavior
3.2. Configuring Intel® MAX® 10 Devices using JTAG Configuration x
3.2.1. Auto-Generating Configuration Files for Third-Party Programming Tools Generating Third-Party Programming Files using Intel® Quartus® Prime Programmer 3.2.3. JTAG Configuration Setup 3.2.4. ICB Settings in JTAG Configuration
3.3. Configuring Intel® MAX® 10 Devices using Internal Configuration x
3.3.1. Selecting Internal Configuration Modes 3.3.2. .pof and ICB Settings 3.3.3. Programming .pof into Internal Flash
3.3.2. .pof and ICB Settings x
3.3.2.1. Auto-Generated .pof 3.3.2.2. Generating .pof using Convert Programming Files Generating Third-Party Programming Files using Intel® Quartus® Prime Programmer
3.4. Implementing ISP Clamp in Intel® Quartus® Prime Software x
3.4.1. Creating IPS File 3.4.2. Executing IPS File
3.6. Error Detection x
3.6.1. Verifying Error Detection Functionality 3.6.2. Enabling Error Detection 3.6.3. Accessing Error Detection Block Through User Logic
3.7. Enabling Data Compression x
3.7.1. Enabling Compression Before Design Compilation 3.7.2. Enabling Compression After Design Compilation
3.8. AES Encryption x
3.8.1. Generating .ekp File and Encrypt Configuration File 3.8.2. Generating .jam/.jbc/.svf file from .ekp file 3.8.3. Programming .ekp File and Encrypted POF File 3.8.4. Encryption in Internal Configuration
3.8.3. Programming .ekp File and Encrypted POF File x
3.8.3.1. Programming .ekp File and Encrypted .pof Separately 3.8.3.2. Integrate the .ekp into .pof Programming
3.9. Intel® MAX® 10 JTAG Secure Design Example x
3.9.1. Internal and External JTAG Interfaces 3.9.2. JTAG WYSIWYG Atom for JTAG Control Block Access Using Internal JTAG Interface 3.9.3. Executing LOCK and UNLOCK JTAG Instructions 3.9.4. Verifying the JTAG Secure Mode
4. Intel® MAX® 10 FPGA Configuration IP Core Implementation Guides x
4.1. Unique Chip ID Intel® FPGA IP Core 4.2. Dual Configuration Intel® FPGA IP Core
4.1. Unique Chip ID Intel® FPGA IP Core x
4.1.1. Instantiating the Unique Chip ID Intel® FPGA IP Core 4.1.2. Resetting the Unique Chip ID Intel® FPGA IP Core
4.2. Dual Configuration Intel® FPGA IP Core x
4.2.1. Instantiating the Dual Configuration Intel® FPGA IP Core
5. Dual Configuration Intel® FPGA IP Core References x
5.1. Dual Configuration Intel® FPGA IP Core Avalon® Memory-Mapped Address Map 5.2. Dual Configuration Intel® FPGA IP Core Parameters
6. Unique Chip ID Intel® FPGA IP Core References x
6.1. Unique Chip ID Intel® FPGA IP Core Ports
1. Intel® MAX® 10 FPGA Configuration Overview
2. Intel® MAX® 10 FPGA Configuration Schemes and Features
3. Intel® MAX® 10 FPGA Configuration Design Guidelines
4. Intel® MAX® 10 FPGA Configuration IP Core Implementation Guides
5. Dual Configuration Intel® FPGA IP Core References
6. Unique Chip ID Intel® FPGA IP Core References
7. Document Revision History for the Intel® MAX® 10 FPGA Configuration User Guide

3.3.2.2. Generating .pof using Convert Programming Files

To convert .sof files to .pof files and to set the ICB using Convert Programming Files, follow these steps:

  1. On the File menu, click Convert Programming Files.
  2. Under Output programming file, select Programmer Object File (.pof) in the Programming file type list.
  3. In the Mode list, select Internal Configuration.
  4. To set the ICB settings, click Option/Boot Info and the Max 10 Device Options dialog box appears. The Max 10 Device Options dialog box allows you to set the following:
    1. User I/Os weak pull up during configuration.
    2. Configure device from CFM0 only.
      Note: When you enable this feature, the device always loads configuration image 0 without sampling the physical CONFIG_SEL pin. After successfully loading configuration image 0, you can switch between configuration images using the config_sel_overwrite bit of the input register. Refer to related information for details about Dual Configuration Intel® FPGA IP input register.
    3. Use secondary image ISP data as default setting when available.
    4. JTAG Secure.
      Note: The JTAG Secure feature is disabled by default in Intel® Quartus® Prime software. To make this option visible in the GUI, you must create a quartus.ini file using the text editor, with the key-value pair: PGM_ENABLE_MAX10_JTAG_SECURITY=ON and save the file in one of the following folders:
      • Project folder.
      • Windows operating system: <Quartus installation folder>\bin64 folder.
      • Linux operating system: <Quartus installation folder>/linux64 folder.
      CAUTION:
      Intel® MAX® 10 FPGA device becomes permanently locked if you enabled JTAG secure mode in the POF file and POF is encrypted with the wrong key. You must instantiate the internal JTAG interface for you unlock the external JTAG when the device is in JTAG Secure mode.
    5. Verify Protect.
    6. Allow encrypted POF only.
    7. Watchdog timer for dual configuration and watchdog timer value (Enabled after adding 2 .sof page with two designs that compiled with Dual Compressed Internal Images).
    8. User Flash Memory settings.
    9. User Data in Configuration Flash Memory (CFM).
      The function is to store user data in unused CFM0/1 space. It can be done by using Convert Programming File (CPF) GUI, command line (quartus_cpf), and the conversion setup file (.cof). CPF reports error messages for cases as shown in the following table:
      Table 29.  CPF Error Messages
      Case Error Message
      if the start address overlaps with configuration data Error (20646): The page CFM0 user data requested start address 0x0014BA00 overlaps with configuration data that end at address 0x0014BA6B.
      if the HEX file cannot fit in unused CFM space Error (20640): Memory file test.hex contains 256 bytes. It cannot fit in CFM0 section which has only 254 bytes unused memory space. Size of file(s) in CFM0 exceeds memory capacity.
      if the start address exceeds the CFM block Error (20648): The page CFM0 user data requested start address 0x00162000 exceeds page end address 0x00161FFF.
      Convert Programming File GUI

      You can specify a starting address and HEX file for insertion into CFM 0/1 in CFM0/1 File path and CFM0/1 start address (32-bit hexadecimal) respectively in the Max 10 Device Options dialog box. The tool automatically allocates an empty space for the HEX file if the start address remains as 0x0.

      You can refer to the memory map file (*.map) to check the start address. The start address is after the end address of CFM0/1. For example, in the figure below, insert your data in CFM0 with start address 0x0014BA6C and end address 0x00161FFF. The .map file is updated with CFM0_DATA start address and end address once you generate the POF file with Create Memory Map enabled.

      Figure 14. Example of Memory Map File (*.map)
      Command Line (quartus_cpf)
      In the command line interface, run the quartus_cpf command with the following syntax: 
      quartus_cpf  -c -o cfm0_source_file=<user>.hex -o cfm0_start_address=<12345678> <user>.sof <user>.pof
      Example of quartus_cpf command: 
      quartus_cpf  -c -o cfm0_source_file=test.hex -o cfm0_start_address=0014BA6C abc.sof abc.pof
      Conversion Setup File (*.cof)
      In the Convert Programming File dialog box, you may save the setting by click the Save Conversion Setup… and edit cfm0_filepath and cfm_ file_start_addr in the <user>.cof file as shown below.
    10. RPD File Endianness.
  5. In the File name box, specify the file name for the programming file you want to create.
  6. To generate a Memory Map File (.map), turn on Create Memory Map File (Auto generate output_file.map). The .map contains the address of the CFM and UFM with the ICB setting that you set through the Option/Boot Info option.
  7. To generate a Raw Programming Data (.rpd), turn on Create config data RPD (Generate output_file_auto.rpd).
    Separate Raw Programming Data (.rpd) for each configuration flash memory and user flash memory (CFM0, CFM1, UFM) section are generated together for remote system upgrade purpose.
  8. The .sof can be added through Input files to convert list and you can add up to two .sof files.
    For remote system upgrade purpose, you can retain the original page 0 data in the .pof, and replace page 1 data with a new .sof file. To perform this, you must to add the .pof file in page 0, then add .sof page, then add the new .sof file to page 1.
  9. After all settings are set, click Generate to generate related programming file.
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