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1. MAX® 10 FPGA Configuration Overview
2. MAX® 10 FPGA Configuration Schemes and Features
3. MAX® 10 FPGA Configuration Design Guidelines
4. MAX® 10 FPGA Configuration IP Core Implementation Guides
5. Dual Configuration Intel® FPGA IP Core References
6. Unique Chip ID Intel® FPGA IP Core References
7. Document Revision History for the MAX® 10 FPGA Configuration User Guide
3.1. Dual-Purpose Configuration Pins
3.2. Configuring MAX® 10 Devices using JTAG Configuration
3.3. Configuring MAX® 10 Devices using Internal Configuration
3.4. Implementing ISP Clamp in Quartus® Prime Software
3.5. Accessing Remote System Upgrade through User Logic
3.6. Error Detection
3.7. Enabling Data Compression
3.8. AES Encryption
3.9. MAX® 10 JTAG Secure Design Example
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2.2.3.3.2. Cyclic Redundancy Check Calculation Timing
Device | Divisor Value (n = 2) | |
---|---|---|
Minimum Time (ms) | Maximum Time (ms) | |
10M02/10M02SCU324 | 2/6 | 6.6/15.7 |
10M04 | 6 | 15.7 |
10M08 | 6 | 15.7 |
10M16 | 10 | 25.5 |
10M25 | 14 | 34.7 |
10M40 | 43 | 106.7 |
10M50 | 43 | 106.7 |
Figure 9. CRC Calculation FormulaYou can use this formula to calculate the CRC calculation time for divisor other than 2.
CRC Calculation Example
For 10M16 device with divisor value of 256:
Minimum CRC calculation time for divisor 256 = 10 x (256/2) = 1280 ms