MAX® 10 FPGA Configuration User Guide

ID 683865
Date 5/14/2025
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2.2.3.3.1. Error Detection Frequency

You can set a lower clock frequency by specifying a division factor in the Quartus® Prime software.
Table 21.  Minimum and Maximum Error Detection Frequencies for MAX® 10 Devices
Device Error Detection Frequency Maximum Error Detection Frequency (MHz) Minimum Error Detection Frequency (kHz) Valid Values for n
10M02 55 MHz/2n to 116 MHz/2n 58 214.8 1, 2, 3, 4, 5, 6, 7, 8
10M04
10M08
10M16
10M25
10M40 35 MHz/2n to 77 MHz/2n 38.5 136.7
10M50