Visible to Intel only — GUID: lbl1440614133596
Ixiasoft
Visible to Intel only — GUID: lbl1440614133596
Ixiasoft
4.7. Example Designs
Parameter |
Value |
Description |
---|---|---|
Available Example Designs |
DMA PIO |
When you select the DMA option, the generated example design includes a direct memory access application. This application includes upstream and downstream transactions. The DMA example design uses the Write Data Mover, Read Data Mover, and a custom Descriptor Controller. When you select the PIO option, the generated design includes a target application including only downstream transactions. |
Simulation | On/Off | When On, the generated output includes a simulation model. |
Synthesis | On/Off | When On, the generated output includes a synthesis model. |
Generated HDL format | Verilog/VHDL |
Only Verilog HDL is available in the current release. |
Target Development Kit | None Stratix® 10 H-Tile ES1 Development Kit Stratix® 10 L-Tile ES2 Development Kit |
Select the appropriate development board.
If you select one of the development boards, system generation overwrites the device you selected with the device on that development board.
Note: If you select None, system generation does not make any pin assignments. You must make the assignments in the .qsf file.
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