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1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Registers
8. Programming Model for the DMA Descriptor Controller
9. Programming Model for the Avalon® -MM Root Port
10. Avalon-MM Testbench and Design Example
11. Document Revision History
A. PCI Express Core Architecture
B. Root Port Enumeration
C. Troubleshooting and Observing the Link Status
2.1. Design Components
2.2. Hardware and Software Requirements
2.3. Directory Structure
2.4. Generating the Design Example
2.5. Simulating the Design Example
2.6. Compiling the Design Example and Programming the Device
2.7. Installing the Linux Kernel Driver
2.8. Running the Design Example Application
7.1.1. Register Access Definitions
7.1.2. PCI Configuration Header Registers
7.1.3. PCI Express Capability Structures
7.1.4. Intel Defined VSEC Capability Header
7.1.5. Uncorrectable Internal Error Status Register
7.1.6. Uncorrectable Internal Error Mask Register
7.1.7. Correctable Internal Error Status Register
7.1.8. Correctable Internal Error Mask Register
7.2.1.1. Avalon-MM to PCI Express Interrupt Status Registers
7.2.1.2. Avalon-MM to PCI Express Interrupt Enable Registers
7.2.1.3. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules
7.2.1.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
7.2.1.5. PCI Express Configuration Information Registers
10.5.1. ebfm_barwr Procedure
10.5.2. ebfm_barwr_imm Procedure
10.5.3. ebfm_barrd_wait Procedure
10.5.4. ebfm_barrd_nowt Procedure
10.5.5. ebfm_cfgwr_imm_wait Procedure
10.5.6. ebfm_cfgwr_imm_nowt Procedure
10.5.7. ebfm_cfgrd_wait Procedure
10.5.8. ebfm_cfgrd_nowt Procedure
10.5.9. BFM Configuration Procedures
10.5.10. BFM Shared Memory Access Procedures
10.5.11. BFM Log and Message Procedures
10.5.12. Verilog HDL Formatting Functions
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B. Root Port Enumeration
This chapter provides a flow chart that explains the Root Port enumeration process.
The goal of enumeration is to find all connected devices in the system and for each connected device, set the necessary registers and make address range assignments.
At the end of the enumeration process, the Root Port (RP) must set the following registers:
- Primary Bus, Secondary Bus and Subordinate Bus numbers
- Memory Base and Limit
- IO Base and IO Limit
- Max Payload Size
- Memory Space Enable bit
The Endpoint (EP) must also have the following registers set by the RP:
- Master Enable bit
- BAR Address
- Max Payload Size
- Memory Space Enable bit
- Severity bit
The figure below shows an example tree of connected devices on which the following flow chart will be based.
Figure 77. Tree of Connected Devices in Example System
Figure 78. Root Port Enumeration Flow Chart
Figure 79. Root Port Enumeration Flow Chart (continued)
Figure 80. Root Port Enumeration Flow Chart (continued)
Notes:
- Vendor ID and Device ID information is located at offset 0x00h for both Header Type 0 and Header Type 1.
- For PCIe Gen4, the Header Type is located at offset 0x0Eh (2nd DW). If bit 0 is set to 1, it indicates the device is a Bridge; otherwise, it is an EP. If bit 7 is set to 0, it indicates this is a single-function device; otherwise, it is a multi-function device.
- List of capability registers for RP and non-RP devices:
- 0x34h – Capabilities Pointers. This register is used to point to a linked list of capabilities implemented by a Function:
- Capabilities Pointer for RP
- Address 40 - Identifies the Power Management Capability ID
- Address 50 - Identifies MSI Capability ID
- Address 70 - Identifies the PCI Express Capability structure
- Capabilities Pointer for non-RP
- Address 40 - Identifies Power Management Capability ID
- Address 70 - Identifies the PCI Express Capability structure
- Capabilities Pointer for RP
- 0x34h – Capabilities Pointers. This register is used to point to a linked list of capabilities implemented by a Function:
- EP does not have an associated register of Primary, Secondary and Subordinate Bus numbers.
- Bridge/Switch IO Base and Limit register offset 0x1Ch. These registers are set per the PCIe 4.0 Base Specification. For more accurate information and flow, refer to chapter 7.5.1.3.6 of the Base Specification.
- For EP Type 0 header, BAR addresses are located at the following offsets:
- 0x10h – Base Address 0
- 0x14h – Base Address 1
- 0x18h – Base Address 2
- 0x1ch – Base Address 3
- 0x20h – Base Address 4
- 0x24h – Base Address 5
- For Bridge/Switch Type 1 header, BAR addresses are located at the following offsets:
- 0x10h – Base Address 0
- 0x14h – Base Address 1
- For Bridge/Switch Type 1 header, IO Base and IO limit registers are located at offset 0x1Ch.
- For Bridge/Switch Type 1 header, Non-Prefetchable Memory Base and Limit registers are located at offset 0x20h.
- For Bridge/Switch Type 1 header, Prefetchable Memory Base and Limit registers are located at offset 0x24h.
- For Bridge/Switch/EP Type 0 & 1 headers, the Bus Master Enable bit is located at offset 0x04h (Command Register) bit 2.
- For Bridge/Switch/EP Type 0 & 1 headers,
- IO Space Enable bit is located at offset 0x04h (Command Register) bit 0.
- Memory Space Enable bit is located at offset 0x04h (Command Register) bit 1.
- Bus Master Enable bit is located at offset 0x04h (Command Register) bit 2.
- Parity Error Response bit is located at offset 0x04h (Command Register) bit 6.
- SERR# Enable bit is located at offset 0x04h (Command Register) bit 8.
- Interrupt Disable bit is located at offset 0x04h (Command Register) bit 10.