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1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Registers
8. Programming Model for the DMA Descriptor Controller
9. Programming Model for the Avalon® -MM Root Port
10. Avalon-MM Testbench and Design Example
11. Document Revision History
A. PCI Express Core Architecture
B. Root Port Enumeration
C. Troubleshooting and Observing the Link Status
2.1. Design Components
2.2. Hardware and Software Requirements
2.3. Directory Structure
2.4. Generating the Design Example
2.5. Simulating the Design Example
2.6. Compiling the Design Example and Programming the Device
2.7. Installing the Linux Kernel Driver
2.8. Running the Design Example Application
7.1.1. Register Access Definitions
7.1.2. PCI Configuration Header Registers
7.1.3. PCI Express Capability Structures
7.1.4. Intel Defined VSEC Capability Header
7.1.5. Uncorrectable Internal Error Status Register
7.1.6. Uncorrectable Internal Error Mask Register
7.1.7. Correctable Internal Error Status Register
7.1.8. Correctable Internal Error Mask Register
7.2.1.1. Avalon-MM to PCI Express Interrupt Status Registers
7.2.1.2. Avalon-MM to PCI Express Interrupt Enable Registers
7.2.1.3. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules
7.2.1.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
7.2.1.5. PCI Express Configuration Information Registers
10.5.1. ebfm_barwr Procedure
10.5.2. ebfm_barwr_imm Procedure
10.5.3. ebfm_barrd_wait Procedure
10.5.4. ebfm_barrd_nowt Procedure
10.5.5. ebfm_cfgwr_imm_wait Procedure
10.5.6. ebfm_cfgwr_imm_nowt Procedure
10.5.7. ebfm_cfgrd_wait Procedure
10.5.8. ebfm_cfgrd_nowt Procedure
10.5.9. BFM Configuration Procedures
10.5.10. BFM Shared Memory Access Procedures
10.5.11. BFM Log and Message Procedures
10.5.12. Verilog HDL Formatting Functions
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5.2. Simulation
The Quartus® Prime Pro Edition software optionally generates a functional simulation model, a testbench or design example, and vendor-specific simulator setup scripts when you generate your parameterized PCI Express* IP core. For Endpoints, the generation creates a Root Port BFM.
Note: Root Port example design generation is not supported in this release of Quartus® Prime Pro Edition.
The Quartus® Prime Pro Edition supports the following simulators.
Vendor | Simulator | Version | Platform |
---|---|---|---|
Aldec | Active-HDL * | 10.3 | Windows |
Aldec | Riviera-PRO * | 2016.10 | Windows, Linux |
Cadence | Incisive Enterprise * (NCSim*) | 15.20 | Linux |
Cadence | Xcelium* Parallel Simulator | 17.04.014 | Linux |
Mentor Graphics | ModelSim PE* | 10.5c | Windows |
Mentor Graphics | ModelSim SE* | 10.5c | Windows, Linux |
Mentor Graphics | QuestaSim* | 10.5c | Windows, Linux |
Synopsys | VCS*/VCS MX* | 2016,06-SP-1 | Linux |
Note: The Intel testbench and Root Port BFM provide a simple method to do basic testing of the Application Layer logic that interfaces to the PCIe IP variation. This BFM allows you to create and run simple task stimuli with configurable parameters to exercise basic functionality of the example design. The testbench and Root Port BFM are not intended to be a substitute for a full verification environment. Corner cases and certain traffic profile stimuli are not covered. To ensure the best verification coverage possible, Intel suggests strongly that you obtain commercially available PCI Express verification IP and tools, or do your own extensive hardware testing or both.