Visible to Intel only — GUID: lbl1465424164077
Ixiasoft
Visible to Intel only — GUID: lbl1465424164077
Ixiasoft
6.1.6.3. Hard IP Status Interface
Signal |
Direction |
Description |
---|---|---|
derr_cor_ext_rcv | Output |
When asserted, indicates that the RX buffer detected a 1-bit (correctable) ECC error. This is a pulse stretched output. |
derr_cor_ext_rpl | Output |
When asserted, indicates that the retry buffer detected a 1-bit (correctable) ECC error. This is a pulse stretched output. |
derr_rpl | Output |
When asserted, indicates that the retry buffer detected a 2-bit (uncorrectable) ECC error. This is a pulse stretched output. |
derr_uncor_ext_rcv | Output |
When asserted, indicates that the RX buffer detected a 2-bit (uncorrectable) ECC error. This is a pulse stretched output. |
int_status[10:0](H-Tile) int_status[7:0] (L-Tile) int_status_pf1[7:0] (L-Tile) |
Output |
The int_status[3:0] signals drive legacy interrupts to the application (for H-Tile). The int_status[10:4] signals provide status for other interrupts (for H-Tile). The int_status[3:0] signals drive legacy interrupts to the application for PF0 (for L-Tile). The int_status[7:4] signals provide status for other interrupts for PF0 (for L-Tile). The int_status_pf1[3:0] signals drive legacy interrupts to the application for PF1 (for L-Tile). The int_status_pf1[7:4] signals provide status for other interrupts for PF1 (for L-Tile). The following signals are defined:
|
int_status_common[2:0] | Output |
Specifies the interrupt status for the following registers. When asserted, indicates that an interrupt is pending:
|
lane_act[4:0] | Output |
Lane Active Mode: This signal indicates the number of lanes that configured during link training. The following encodings are defined:
|
link_up | Output |
When asserted, the link is up. |
ltssmstate[5:0] | Output |
Link Training and Status State Machine (LTSSM) state: The LTSSM state machine encoding defines the following states:
|
rx_par_err | Output |
Asserted for a single cycle to indicate that a parity error was detected in a TLP at the input of the RX buffer. This error is logged as an uncorrectable internal error in the VSEC registers. For more information, refer to Uncorrectable Internal Error Status Register. If this error occurs, you must reset the Hard IP because parity errors can leave the Hard IP in an unknown state. |
tx_par_err | Output |
Asserted for a single cycle to indicate a parity error during TX TLP transmission. The IP core transmits TX TLP packets even when a parity error is detected. |