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1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Registers
8. Programming Model for the DMA Descriptor Controller
9. Programming Model for the Avalon® -MM Root Port
10. Avalon-MM Testbench and Design Example
11. Document Revision History
A. PCI Express Core Architecture
B. Root Port Enumeration
C. Troubleshooting and Observing the Link Status
2.1. Design Components
2.2. Hardware and Software Requirements
2.3. Directory Structure
2.4. Generating the Design Example
2.5. Simulating the Design Example
2.6. Compiling the Design Example and Programming the Device
2.7. Installing the Linux Kernel Driver
2.8. Running the Design Example Application
7.1.1. Register Access Definitions
7.1.2. PCI Configuration Header Registers
7.1.3. PCI Express Capability Structures
7.1.4. Intel Defined VSEC Capability Header
7.1.5. Uncorrectable Internal Error Status Register
7.1.6. Uncorrectable Internal Error Mask Register
7.1.7. Correctable Internal Error Status Register
7.1.8. Correctable Internal Error Mask Register
7.2.1.1. Avalon-MM to PCI Express Interrupt Status Registers
7.2.1.2. Avalon-MM to PCI Express Interrupt Enable Registers
7.2.1.3. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules
7.2.1.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
7.2.1.5. PCI Express Configuration Information Registers
10.5.1. ebfm_barwr Procedure
10.5.2. ebfm_barwr_imm Procedure
10.5.3. ebfm_barrd_wait Procedure
10.5.4. ebfm_barrd_nowt Procedure
10.5.5. ebfm_cfgwr_imm_wait Procedure
10.5.6. ebfm_cfgwr_imm_nowt Procedure
10.5.7. ebfm_cfgrd_wait Procedure
10.5.8. ebfm_cfgrd_nowt Procedure
10.5.9. BFM Configuration Procedures
10.5.10. BFM Shared Memory Access Procedures
10.5.11. BFM Log and Message Procedures
10.5.12. Verilog HDL Formatting Functions
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10.1. Avalon-MM Endpoint Testbench
You can generate the testbench from the example design by following the instructions in Quick Start Guide.
Figure 68. Design Example for Endpoint Designs
The Root Port BFM includes the following top-level modules in the <testbench_dir/pcie_<dev>_hip_avmm_bridge_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/DUT_pcie_tb_ip/altera_pcie_s10_tbed_<ver>/sim directory:
- altpcietb_bfm_top_rp.sv: This is the Root Port PCI Express BFM. For more information about this module, refer to Root Port BFM.
- altpcietb_bfm_rp_gen3_x8.sv: This module drives transactions to the Root Port BFM. The main process operates in two stages:
- First, it configures the Endpoint using the task ebfm_cfg_rp_eg.
- Second, it runs a memory access test with the task target_mem_test or target_mem_test_lite.
- Finally, it runs a DMA test with the task dma_mem_test.
- altpcietb_bfm_shmem.v: This memory implements the following functionality:
- Provides data for TX write operations
- Provides data for RX read operations
- Receives data for RX write operations
- Receives data for received completions
In addition, the testbench has routines that perform the following tasks:
- Generates the reference clock for the Endpoint at the required frequency.
- Provides a PCI Express reset at start up.
Note: Before running the testbench, you should set the serial_sim_hwtcl parameter in <testbench_dir>/pcie_ed_tb/ip/pcie_ed_tb/DUT_pcie_tb_ip/sim/DUT_pcie_tb_ip.v. Set to 1 for serial simulation and 0 for PIPE simulation.
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