Visible to Intel only — GUID: tco1470866831511
Ixiasoft
Visible to Intel only — GUID: tco1470866831511
Ixiasoft
11.1. Document Revision History for the L-Tile and H-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide
Document Version | Quartus® Prime Version | Changes |
---|---|---|
2024.09.13 | 23.4 | Added Notes with reset recommendations to the Resets section. |
2024.03.05 | 23.4 | Added additional information for Questa Intel FPGA Edition in Steps to Run Simulation table in Simulating the Design Example section. |
2023.04.03 | 23.1 | Changed the IP name from Intel® L-/H-Tile Avalon® memory mapped IP for PCI Express* to L-/H-Tile Avalon® Memory-Mapped Intel® FPGA IP for PCI Express* . The Quartus® Prime Platform Designer has been updated to give an explicit warning when the input BAR size exceeds the limit. |
2021.11.11 | 21.1 | Removed references to the 64-bit Application interface data width from all chapters since only the 256-bit interface width is supported. |
2021.10.19 | 21.1 | Changed the device support level for Stratix® 10 to Final Support in the Device Family Support section. |
2021.05.27 | 21.1 | Added an Appendix chapter on Root Port enumeration. Added a note to the Features section stating that L- and H-tile Avalon® Memory-mapped IP for PCI Express only supports the Separate Reference Clock With No Spread Spectrum architecture (SRNS), but not the Separate Reference Clock With Independent Spread Spectrum architecture (SRIS). |
2021.04.12 | 20.3 | Added a note to the Features and Generating the Design Example sections stating that pin allocations for this IP cannot be changed in the Quartus® Prime project, but the IP does support lane reversal and polarity inversion on the PCB by default. |
2020.10.05 | 20.3 | Updated the IP name to Intel L-/H-tile Avalon Memory-mapped IP for PCI Express. Removed the Simple DMA design example option from the Generating the Design Example section as that design example is no longer available. Added a note to the Read Data Mover section stating that Completion TLPs are restricted to a data payload of up to 256 bytes. |
2020.06.03 | 20.1 | Added the description for the new input ninit_done to the Resets section under Clocks and Resets. Also added a link to AN 891: Using the Reset Release Intel FPGA IP, which describes the Reset Release IP that is used to drive the ninit_done input. |
2020.05.11 | 20.1 | Changed the Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME). |
2020.04.23 | 19.3 | Updated the ready latency value in section Avalon® -ST Descriptor Source from 3 cycles to 1 cycle. |
2020.04.22 | 19.3 | Updated the document title to Stratix® 10 H-Tile and L-Tile Avalon® memory mapped Hard IP for PCI Express* User Guide to meet new legal naming guidelines. Fixed a typo in the byte address of some Reserved bits in Table 51. Correspondence between Configuration Space Capability Structures and the PCIe Base Specification Description. |
2020.03.25 | 19.3 | Added notes stating that the Hard IP Reconfiguration interface is not accessible if the PCIe Link Inspector is enabled to the System Interfaces and Hard IP Reconfiguration Interface sections. |
2020.01.03 | 19.3 | Updated resource utilization numbers for the Gen1 x1 variant. Added notes stating that the Gen3 x16 variant is supported by the Stratix® 10 Avalon® Memory Mapped (Avalon-MM) Hard IP+ for PCI Express* . |
2019.09.30 | 19.3 | Added a note to clarify that this User Guide is applicable to H-Tile and L-Tile variants of the Stratix® 10 devices only. Added Autonomous Hard IP mode to the Features section. |
2019.07.18 | 19.1 | Added a note stating that refclk must be stable and free-running at device power-up for a successful device configuration. |
2019.03.30 | 19.1 | Added a chapter on the programming model for Root Ports. Removed the note stating that Root Port mode is not recommended. Removed the BIOS Enumeration section from the Troubleshooting chapter. |
2019.03.12 | 18.1.1 | Updated the E-Tile PAM-4 frequency to 57.8G and NRZ frequency to 28.9G. |
2019.03.04 | 18.1.1 | Updated the commands to run VCS, NCSim and Xcelium simulations in the Simulating the Design Example topic. |
2018.12.24 | 18.1.1 | Added the description for the Link Inspector Avalon® -MM Interface. Added the Avalon® -MM-to-PCIe rxm_irq for MSI feature. |
2018.10.26 | 18.1 | Added the statements that the IP core does not support the L1/L2 low-power states, the in-band beacon and sideband WAKE# signal. |
2018.09.24 | 18.1 | Added the ltssm_file2console and ltssm_save_oldstates commands for the PCIe* Link Inspector. Updated the steps to run ModelSim simulations for a design example. Updated the steps to run a design example. |
2018.08.29 | 18.0 | Added the step to invoke vsim to the instructions for running a ModelSim simulation. |
Date | Version | Changes |
---|---|---|
May 2018 | 18.0 | Made the following changes to the user guide:
|
November 2017 | 17.1 | Removed Enable RX-polarity inversion in soft logic parameter. This parameter is not required for Stratix® 10 devices. |
November 2017 | 17.1 | Made the following changes to the user guide:
Made the following changes to the Stratix® 10 hard IP for PCI Express* IP core:
|
May 2017 | Quartus®Prime Pro v17.1 Stratix 10 ES Editions Software | Made the following changes to the IP core:
Made the following changes to the user guide:
|
October 2016 | Quartus® Prime Pro – Stratix 10 Edition Beta | Initial release |