Visible to Intel only — GUID: lbl1465600497937
Ixiasoft
Visible to Intel only — GUID: lbl1465600497937
Ixiasoft
6.1.6.4. Hard IP Reconfiguration
If the PCIe Link Inspector is enabled, accesses via the Hard IP Reconfiguration interface are not supported. The Link Inspector exclusively uses the Hard IP Reconfiguration interface, and there is no arbitration between the Link Inspector and the Hard IP Reconfiguration interface that is exported to the top level of the IP.
Signal |
Direction |
Description |
---|---|---|
hip_reconfig_clk | Input |
Reconfiguration clock. The frequency range for this clock is 100–125 MHz. |
hip_reconfig_rst_n | Input |
Active-low Avalon-MM reset for this interface. |
hip_reconfig_address[20:0] | Input |
The 21‑bit reconfiguration address. When the Hard IP reconfiguration feature is enabled, the hip_reconfig_address[20:0] bits are programmable. Some bits have the same functions in both H-Tile and L-Tile:
Some bits have different functions in H-Tile versus L-Tile: For H-Tile:
For L-Tile:
|
hip_reconfig_read | Input |
Read signal. This interface is not pipelined. You must wait for the return of the hip_reconfig_readdata[7:0] from the current read before starting another read operation. |
hip_reconfig_readdata[7:0] | Output |
8‑bit read data. hip_reconfig_readdata[7:0] is valid on the third cycle after the assertion of hip_reconfig_read. |
hip_reconfig_readdatavalid | Output | When asserted, the data on hip_reconfig_readdata[7:0] is valid. |
hip_reconfig_write | Input |
Write signal. |
hip_reconfig_writedata[7:0] | Input |
8‑bit write model. |
hip_reconfig_waitrequest | Output | When asserted, indicates that the IP core is not ready to respond to a request. |