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1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Registers
8. Programming Model for the DMA Descriptor Controller
9. Programming Model for the Avalon® -MM Root Port
10. Avalon-MM Testbench and Design Example
11. Document Revision History
A. PCI Express Core Architecture
B. Root Port Enumeration
C. Troubleshooting and Observing the Link Status
2.1. Design Components
2.2. Hardware and Software Requirements
2.3. Directory Structure
2.4. Generating the Design Example
2.5. Simulating the Design Example
2.6. Compiling the Design Example and Programming the Device
2.7. Installing the Linux Kernel Driver
2.8. Running the Design Example Application
7.1.1. Register Access Definitions
7.1.2. PCI Configuration Header Registers
7.1.3. PCI Express Capability Structures
7.1.4. Intel Defined VSEC Capability Header
7.1.5. Uncorrectable Internal Error Status Register
7.1.6. Uncorrectable Internal Error Mask Register
7.1.7. Correctable Internal Error Status Register
7.1.8. Correctable Internal Error Mask Register
7.2.1.1. Avalon-MM to PCI Express Interrupt Status Registers
7.2.1.2. Avalon-MM to PCI Express Interrupt Enable Registers
7.2.1.3. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules
7.2.1.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
7.2.1.5. PCI Express Configuration Information Registers
10.5.1. ebfm_barwr Procedure
10.5.2. ebfm_barwr_imm Procedure
10.5.3. ebfm_barrd_wait Procedure
10.5.4. ebfm_barrd_nowt Procedure
10.5.5. ebfm_cfgwr_imm_wait Procedure
10.5.6. ebfm_cfgwr_imm_nowt Procedure
10.5.7. ebfm_cfgrd_wait Procedure
10.5.8. ebfm_cfgrd_nowt Procedure
10.5.9. BFM Configuration Procedures
10.5.10. BFM Shared Memory Access Procedures
10.5.11. BFM Log and Message Procedures
10.5.12. Verilog HDL Formatting Functions
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2.8. Running the Design Example Application
- Navigate to ./software/user/example under the design example directory.
- Compile the design example application:
$ make
- Run the test:
$ sudo ./intel_fpga_pcie_link_test
You can run the Intel® FPGA IP PCIe* link test in manual or automatic mode.
- In automatic mode, the application automatically selects the device. The test selects the Stratix® 10 PCIe* device with the lowest BDF by matching the Vendor ID. The test also selects the lowest available BAR.
- In manual mode, the test queries you for the bus, device, and function number and BAR.
For the Stratix® 10 GX Development Kit, you can determine the BDF by typing the following command:$ lspci -d 1172
- Here are sample transcripts for automatic and manual modes:
Intel FPGA PCIe Link Test - Automatic Mode Version 2.0 0: Automatically select a device 1: Manually select a device *************************************************** >0 Opened a handle to BAR 0 of a device with BDF 0x100 *************************************************** 0: Link test - 100 writes and reads 1: Write memory space 2: Read memory space 3: Write configuration space 4: Read configuration space 5: Change BAR 6: Change device 7: Enable SR-IOV 8: Do a link test for every enabled virtual function belonging to the current device 9: Perform DMA 10: Quit program *************************************************** > 0 Doing 100 writes and 100 reads . . Number of write errors: 0 Number of read errors: 0 Number of DWORD mismatches: 0
Intel FPGA PCIe Link Test - Manual Mode Version 1.0 0: Automatically select a device 1: Manually select a device *************************************************** > 1 Enter bus number: > 1 Enter device number: > 0 Enter function number: > 0 BDF is 0x100 Enter BAR number (-1 for none): > 4 Opened a handle to BAR 4 of a device with BDF 0x100
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