Visible to Intel only — GUID: rec1508449447894
Ixiasoft
Visible to Intel only — GUID: rec1508449447894
Ixiasoft
6.1.2.4. Bursting Slave Module
The slave module supports a single outstanding non-bursting request. It typically sends status updates to the host. This is a 32-bit Avalon-MM slave interface.
Signal Name |
Direction |
Description |
---|---|---|
hptxs_read_i |
Input |
When asserted, specifies an Avalon-MM slave. |
hptxs_write_i |
Input |
When asserted, specifies an Avalon-MM slave. |
hptxs_writedata_i[31:0] |
Input |
Specifies the Avalon-MM data for a write command. |
hptxs_address_i[<w>-1:0] |
Input |
Specifies the Avalon-MM byte address for the read or write command. The width of this address bus is specified by the parameter Address width of accessible PCIe memory space (HPTXS). <w> <= 63. |
hptxs_byteenable_i[31:0] |
Input |
Specifies the valid dwords for a write command. |
hptxs_readdata_o[255:0] |
Output |
Drives the read completion data. |
hptxs_readdatavalid_o |
Output |
When asserted, indicates that read data is valid. |
hptxs_waitrequest_o |
Output |
When asserted, indicates that the Avalon-MM slave port is not ready to respond to a read or write request. The non-bursting Avalon-MM slave may asserthptxs_waitrequest_o during idle cycles. An Avalon-MM master may initiate a transaction when hptxs_waitrequest_o is asserted and wait for that signal to be deasserted. |