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1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Registers
8. Programming Model for the DMA Descriptor Controller
9. Programming Model for the Avalon® -MM Root Port
10. Avalon-MM Testbench and Design Example
11. Document Revision History
A. PCI Express Core Architecture
B. Root Port Enumeration
C. Troubleshooting and Observing the Link Status
2.1. Design Components
2.2. Hardware and Software Requirements
2.3. Directory Structure
2.4. Generating the Design Example
2.5. Simulating the Design Example
2.6. Compiling the Design Example and Programming the Device
2.7. Installing the Linux Kernel Driver
2.8. Running the Design Example Application
7.1.1. Register Access Definitions
7.1.2. PCI Configuration Header Registers
7.1.3. PCI Express Capability Structures
7.1.4. Intel Defined VSEC Capability Header
7.1.5. Uncorrectable Internal Error Status Register
7.1.6. Uncorrectable Internal Error Mask Register
7.1.7. Correctable Internal Error Status Register
7.1.8. Correctable Internal Error Mask Register
7.2.1.1. Avalon-MM to PCI Express Interrupt Status Registers
7.2.1.2. Avalon-MM to PCI Express Interrupt Enable Registers
7.2.1.3. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules
7.2.1.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
7.2.1.5. PCI Express Configuration Information Registers
10.5.1. ebfm_barwr Procedure
10.5.2. ebfm_barwr_imm Procedure
10.5.3. ebfm_barrd_wait Procedure
10.5.4. ebfm_barrd_nowt Procedure
10.5.5. ebfm_cfgwr_imm_wait Procedure
10.5.6. ebfm_cfgwr_imm_nowt Procedure
10.5.7. ebfm_cfgrd_wait Procedure
10.5.8. ebfm_cfgrd_nowt Procedure
10.5.9. BFM Configuration Procedures
10.5.10. BFM Shared Memory Access Procedures
10.5.11. BFM Log and Message Procedures
10.5.12. Verilog HDL Formatting Functions
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6.1.3.2. Resets
The PCIe Hard IP generates the reset signal. The Avalon-MM DMA bridge has a single, active low reset input. It is a synchronized version of the reset from the PCIe IP core.
Figure 47. Clock and Reset Connections
Signal |
Direction |
Description |
---|---|---|
app_nreset_status | Output | This is active low reset signal. It is derived from npor or pin_perstn. You can use this signal to reset the Application. |
currentspeed[1:0] | Output | Indicates the current speed of the PCIe link. The following encodings are defined:
|
npor | Input |
The Application Layer drives this active low reset signal. npor resets the entire IP core, PCS, PMA, and PLLs. npor should be held for a minimum of 20 ns. This signal is edge, not level sensitive; consequently, a low value on this signal does not hold custom logic in reset. This signal cannot be disabled. |
pin_perst | Input |
Active low reset from the PCIe reset pin of the device. Resets the datapath and control registers. |
ninit_done | Input | This is an active-low asynchronous input. A "1" on this signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode. To use the ninit_done input, instantiate the Reset Release Intel FPGA IP in your design and use its ninit_done output to drive the input of the Avalon® memory mapped IP for PCIe. |
Note: If FLR is active or has yet to complete, avoid performing a warm reset or asserting pin_perst. Otherwise, the PCIe link may become unstable and will not be able to recover without a cold reset.
Note: The minimum interval time required between two consecutive pin_perst's or hot resets is 60us to ensure link stability. More specifically, the deassertion of pin_perst or hot reset, and the assertion of the next pin_perst or hot reset should be separated by at least 60us.