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1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Registers
8. Programming Model for the DMA Descriptor Controller
9. Programming Model for the Avalon® -MM Root Port
10. Avalon-MM Testbench and Design Example
11. Document Revision History
A. PCI Express Core Architecture
B. Root Port Enumeration
C. Troubleshooting and Observing the Link Status
2.1. Design Components
2.2. Hardware and Software Requirements
2.3. Directory Structure
2.4. Generating the Design Example
2.5. Simulating the Design Example
2.6. Compiling the Design Example and Programming the Device
2.7. Installing the Linux Kernel Driver
2.8. Running the Design Example Application
7.1.1. Register Access Definitions
7.1.2. PCI Configuration Header Registers
7.1.3. PCI Express Capability Structures
7.1.4. Intel Defined VSEC Capability Header
7.1.5. Uncorrectable Internal Error Status Register
7.1.6. Uncorrectable Internal Error Mask Register
7.1.7. Correctable Internal Error Status Register
7.1.8. Correctable Internal Error Mask Register
7.2.1.1. Avalon-MM to PCI Express Interrupt Status Registers
7.2.1.2. Avalon-MM to PCI Express Interrupt Enable Registers
7.2.1.3. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules
7.2.1.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
7.2.1.5. PCI Express Configuration Information Registers
10.5.1. ebfm_barwr Procedure
10.5.2. ebfm_barwr_imm Procedure
10.5.3. ebfm_barrd_wait Procedure
10.5.4. ebfm_barrd_nowt Procedure
10.5.5. ebfm_cfgwr_imm_wait Procedure
10.5.6. ebfm_cfgwr_imm_nowt Procedure
10.5.7. ebfm_cfgrd_wait Procedure
10.5.8. ebfm_cfgrd_nowt Procedure
10.5.9. BFM Configuration Procedures
10.5.10. BFM Shared Memory Access Procedures
10.5.11. BFM Log and Message Procedures
10.5.12. Verilog HDL Formatting Functions
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C.2.1.2. Launching the PCIe* Link Inspector
Use the design example you compiled in the Quick Start Guide, to familiarize yourself with the PCIe* Link Inspector. Follow the steps in the Generating the Avalon® -ST Design or Generating the Avalon® -MM Design and Compiling the Design to generate the SRAM Object File, (.sof) for this design example.
To use the PCIe* Link Inspector, download the .sof to the Stratix® 10 Development Kit. Then, open the System Console on the test PC and load the design to the System Console as well. Loading the .sof to the System Console allows the System Console to communicate with the design using NPDME. NPDME is a JTAG-based Avalon® -MM master. It drives an Avalon® -MM slave interfaces in the PCIe* design. When using NPDME, the Quartus® Prime software inserts the debug interconnect fabric to connect with JTAG.
Here are the steps to complete these tasks:
- Use the Quartus® Prime Programmer to download the .sof to the Stratix® 10 FPGA Development Kit.
Note: To ensure that you have the correct operation, you must use the same version of the Quartus® Prime Programmer and Quartus® Prime Pro Edition software that you used to generate the .sof.
- To load the design to the System Console:
- Launch the Quartus® Prime Pro Edition software on the test PC.
- Start the System Console, Tools > System Debugging Tools > System Console.
- On the System Console File menu, select Load design and browse to the .sof file.
- Select the .sof and click OK.
The .sof loads to the System Console.
- In the System Console Tcl console, type the following commands:
% cd <project_dir>/ip/pcie_example_design/ pcie_example_design_DUT/altera_pcie_s10_hip_ast_<version>/synth/altera_pcie_s10_link_inspector % source TCL/setup_adme.tcl % source TCL/xcvr_pll_test_suite.tcl % source TCL/pcie_link_inspector.tcl
The source TCL/pcie_link_inspector.tcl command automatically outputs the current status of the PCIe* link to the Tcl Console. The command also loads all the PCIe* Link Inspector functionality.
Figure 86. Using the Tcl Console to Access the PCIe* Link Inspector