Visible to Intel only — GUID: zim1468340688051
Ixiasoft
Visible to Intel only — GUID: zim1468340688051
Ixiasoft
5.4. Channel Layout and PLL Usage
The following figures show the channel layout and PLL usage for Gen1, Gen2 and Gen3, x1, x2, x4, x8 and x16 variants of the Intel L-/H-Tile Avalon-MM for PCI Express IP core. Note that the missing variant Gen3 x16 is supported by another IP core (the Intel L-/H-Tile Avalon-MM+ for PCI Express IP core). For more details on the Avalon® -MM+ IP core, refer to https://www.intel.com/content/www/us/en/programmable/documentation/sox1520633403002.html.
The channel layout is the same for the Avalon® -ST and Avalon® -MM interfaces to the Application Layer.