Visible to Intel only — GUID: zno1469208544160
Ixiasoft
Visible to Intel only — GUID: zno1469208544160
Ixiasoft
1.7. Transceiver Tiles
Tile | Device Type | Channel Capability | Channel Hard IP Access | |
---|---|---|---|---|
Chip-to-Chip | Backplane | |||
L-Tile | GX | 26 Gbps (NRZ) | 12.5 Gbps (NRZ) | PCIe Gen3x16 |
H-Tile | GX | 28.3 Gbps (NRZ) | 28.3 Gbps (NRZ) | PCIe Gen3x16 |
E-Tile | GXE | 30 Gbps (NRZ), 56 Gbps (PAM-4) |
30 Gbps (NRZ), 56 Gbps (PAM-4) |
100G Ethernet |
L-Tile and H-Tile
Both L and H transceiver tiles contain four transceiver banks-with a total of 24 duplex channels, eight ATX PLLs, eight fPLLs, eight CMU PLLs, a PCIe Hard IP block, and associated input reference and transmitter clock networks. L and H transceiver tiles also include 10GBASE-KR/40GBASE-KR4 FEC block in each channel.
L-Tiles have transceiver channels that support up to 26 Gbps chip-to-chip or 12.5 Gbps backplane applications. H-Tiles have transceiver channels to support 28 Gbps applications. H-Tile channels support fast lock-time for Gigabit-capable passive optical network (GPON).
Stratix® 10 GX/SX devices incorporate L-Tiles or H-Tiles. Package migration is available with Stratix® 10 GX/SX from L-Tile to H-Tile variants.
E-Tile
E-Tiles are designed to support 56 Gbps with PAM-4 signaling or up to 30 Gbps backplane with NRZ signaling. E-Tiles do not include any PCIe* Hard IP blocks.