Visible to Intel only — GUID: spr1470758112056
Ixiasoft
Visible to Intel only — GUID: spr1470758112056
Ixiasoft
3.3.1. Avalon-MM Master Interfaces
Up to six Avalon-MM Master interfaces can be enabled at configuration time, one for each of the six supported BARs. Each of the enabled Avalon-MM Master interfaces can be set to be bursting or non-bursting in the component GUI. Bursting Avalon-MM Masters are designed for high throughput transfers, and the application interface data bus width is 256-bit. Non-bursting Avalon-MM Masters are designed for small transfers requiring finer granularity for byte enable control, or for control of 32-bit Avalon-MM Slaves. The prefix for signals comprising this interface is rxm_bar<bar_num>*.
Avalon-MM Master Type | Data Bus Width | Max Burst Size | Byte Enable Granularity | Maximum Outstanding Read Requests |
---|---|---|---|---|
Non-bursting | 32-bit | 1 cycle | Byte | 1 |
Bursting | 256-bit | 16 cycles | DWord4 | 32 |