Visible to Intel only — GUID: zxp1468882020342
Ixiasoft
Visible to Intel only — GUID: zxp1468882020342
Ixiasoft
1.1. Avalon-MM Interface for PCIe
Stratix® 10 FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with PCI Express Base Specification 3.0. This IP core combines the functionality of previous Avalon® Memory-Mapped (Avalon-MM) and Avalon-MM direct memory access (DMA) interfaces. It supports the same functionality for Stratix® 10 as the Avalon® -MM and Avalon® -MM with DMA variants for Arria® 10 devices.
The Intel L-/H-Tile Avalon-MM for PCI Express IP core using the Avalon® -MM interface removes many of the complexities associated with the PCIe protocol. It handles all of the Transaction Layer Packet (TLP) encoding and decoding, simplifying the design task. This IP core also includes optional Read and Write Data Mover modules facilitating the creation of high-performance DMA designs. Both the Avalon® -MM interface and the Read and Write Data Mover modules are implemented in soft logic.
The Intel L-/H-Tile Avalon-MM for PCI Express IP Core supports Gen1, Gen2 and Gen3 data rates and x1, x2, x4, and x8 configurations. Gen1 and Gen2 data rates are also supported with the x16 configuration.
Link Width | |||||
---|---|---|---|---|---|
×1 | ×2 | ×4 | ×8 | ×16 | |
PCI Express Gen1 (2.5 Gbps) |
2 |
4 |
8 |
16 |
32 |
PCI Express Gen2 (5.0 Gbps) |
4 |
8 |
16 |
32 |
64 |
PCI Express Gen3 (8.0 Gbps) |
7.87 |
15.75 |
31.5 |
63 |
Not available in current release |