Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

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ID 683645
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide 2. Developing Your Custom Platform 3. Stratix V Network Reference Platform Design Architecture A. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide x
1.1. Stratix V Network Reference Platform: Prerequisites 1.2. Features of the Stratix V Network Reference Platform 1.3. Contents of the Stratix V Network Reference Platform
1.1. Stratix V Network Reference Platform: Prerequisites x
1.1.1. Legacy Board Support
2. Developing Your Custom Platform x
2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
2.4. Setting up the Software Development Environment x
2.4.1. Setting Up Software Development Environment for Windows 2.4.2. Setting Up the Software Development Environment for Linux
3. Stratix V Network Reference Platform Design Architecture x
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
3.1. Host-FPGA Communication over PCIe x
3.1.1. Parameter Settings for PCIe Instantiation 3.1.2. PCIe Device Identification Registers 3.1.3. Version ID 3.1.4. Definitions of Hardware Constants in Software Header Files 3.1.5. PCIe Kernel Driver 3.1.6. SG-DMA
3.2. DDR3 as Global Memory for OpenCL Applications x
3.2.1. DDR3 IP Instantiation 3.2.2. DDR3 Connection to PCIe Host 3.2.3. DDR3 Connection to OpenCL Kernel
3.5. Implementation of UDP Cores as OpenCL Channels x
3.5.1. QuickUDP IP Instantiation 3.5.2. QuickUDP Configuration via PCIe-Based Host 3.5.3. QuickUDP Connection to OpenCL Kernel
3.6. FPGA System Design x
3.6.1. Clocks 3.6.2. Resets 3.6.3. Floorplan 3.6.4. Global Routing 3.6.5. Pipelining 3.6.6. Encrypted IPs
3.7. Guaranteed Timing Closure x
3.7.1. Supply the Kernel Clock 3.7.2. Guarantee Kernel Clock Timing 3.7.3. Provide a Timing-Closed Post-Fit Netlist
3.9. Connection to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe s5_net to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the s5_net Hardware to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow x
3.10.1. CvP 3.10.2. Flash 3.10.3. Defining the Contents of the fpga.bin File
3.10.1. CvP x
3.10.1.1. Replacing FPGA Core Logic via CvP Programming 3.10.1.2. Specifying Configuration via PCI Express Options 3.10.1.3. Base versus CvP Update Revisions in CvP Programming
3.12. OpenCL Utilities Implementation x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide
2. Developing Your Custom Platform
3. Stratix V Network Reference Platform Design Architecture
A. Document Revision History

3.11. Host-to-Device MMD Software Implementation

The MMD layer is a thin software layer for communicating with the board. A full implementation of the MMD library is necessary for every Custom Platform for the proper functioning of the OpenCL™ host applications and board utilities. Details of the API functions, their arguments, and return values for MMD layer are specified in the <TOP_DEST_DIR>/source/include/aocl_mmd.h file, where <TOP_DEST_DIR> points to the top-level directory of your Custom Platform.

The source codes of an MMD library that demonstrates good performance are available in the <TOP_DEST_DIR>/source/host/mmd directory. For more information on the MMD API functions, refer to the MMD API Descriptions section of the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide.

acl_pcie.cpp

The acl_pcie.cpp file implements the MMD API and provides multiple devices support. This file also handles the PCIe® interrupt. For Linux, the kernel driver uses signal to notify the MMD about an interrupt from the PCIe. For Windows, the MMD use the Jungo WinDriver API to handle the interrupt from PCIe.

In addition, this file includes a signal handler for Ctrl-C event. The MMD needs to capture the Ctrl-C event to ensure that the program does not terminate itself during unsafe operation, such as programming the device or running quartus_pgm.

acl_pcie_device.cpp

The acl_pcie_device.cpp file implements a class to represent a device, and abstracts details to allow easier handling of multiple devices. Examples of the supported operations of the device by this class include write_block, read_block, reprogram, and flash.

During the instantiation of an instant for the device class, the following verifications take place:

  1. Ensures that the kernel driver is installed and that its version matches the MMD version.
  2. Ensures that the device with the given name can be found.
  3. Ensures that the Version ID of the device matches the supported ID in the software.
  4. Waits for UniPHY IP calibration.

acl_pcie_mm_io.cpp

The acl_pcie_mm_io.cpp file implements a class to allow access to the device as a memory-mapped I/O. It provides access to GLOBAL-MEM, PCIE-CRA, DMA-CSR, DMA-DESCRIPTOR, KERNEL, etc.

acl_pcie_dma_linux.cpp or acl_pcie_dma_windows.cpp

The acl_pcie_dma_linux.cpp or acl_pcie_dma_windows.cpp file implements DMA-related functions. For more information, refer to the SG-DMA section.

acl_pcie_config.cpp

The acl_pcie_config.cpp file implements functions for configuring the device. For more information, refer to the FPGA Programming Flow section.

acl_pcie_flash.cpp

The acl_pcie_flash.cpp file implements Flash-related functions. For more information, refer to the Flash section.

acl_pcie_quickudp.cpp

The acl_pcie_quickudp.cpp file implements UDP-related functions. For more information, refer to the Implementation of UDP Cores as OpenCL Channels section.

acl_pcie_debug.cpp

The acl_pcie_debug.cpp file defines the commonly used debug functions and parameters. It is included by most of the other files.

acl_pcie_timer.cpp

The acl_pcie_timer.cpp file implements a timer module to measure performance.

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