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2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
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3.6.1. Clocks
The following clock domains affect the Platform Designer (Standard) hardware system:
- 250 MHz PCIe® clock
- 200 MHz DDR3 clock
- 275 MHz QDR clock
- 156.25 MHz Ethernet clock
- 100 MHz general clock (config_clk)
- Kernel clock that can take on any clock frequency
With the exception of the kernel clock, the Stratix® V Network Reference Platform is responsible for closing timing of these clocks. However, because the board design must clock cross all interfaces in the kernel clock domain, the board design also has logic in this clock domain. It is crucial that this logic is minimal and achieves an Fmax higher than typical kernel performance.
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