Visible to Intel only — GUID: ewa1405096723404
Ixiasoft
Visible to Intel only — GUID: ewa1405096723404
Ixiasoft
3.7.3. Provide a Timing-Closed Post-Fit Netlist
- Timing preservation
- Version compatibility to allow the import of the netlist into a newer Intel® Quartus® Prime software version
- Strict preservation of the FPGA periphery to guarantee successful CvP programming
The Intel® FPGA CvP compilation flow for the Stratix V device provides all of these features through an exported .personax file for the top-level partition. This means s5_net is configured with the project revisions and partitions necessary for implementing this flow. By default, the Intel® FPGA SDK for OpenCL™ invokes the Intel® Quartus® Prime software on revision top. This revision is configured to import the persona/base.root_partition.personax file, which has been precompiled and exported from a base revision compilation.
For more information, refer to the CvP section.