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2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
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3.13. Stratix V Network Reference Platform Implementation Considerations
The implementation of the Stratix® V Network Reference Platform includes some workarounds that address certain Intel® Quartus® Prime software known issues.
- The quartus_map executable reads the SDC files. However, it does not support the Tcl command get_current_revision. Therefore, in the top_post.sdc file, a check is in place to determine whether quartus_map has read the file before checking the current version.
- Configuration via PCIe® requires the force_hrc parameter to have a value of 1, and the inclusion of the three PCIe INI settings described in the CvP section.
- The kernel clock requires a lot of connectivity. Therefore, Intel® recommends compiling the base revision using the super_kernel_clock.rcf Routing Constraints File.
- Use the INI setting bpm_hard_block_partition=off to improve version compatibility.
- Use the INI setting qic_pf_no_input_rotation=on to prevent certain failures to route.
- The CvP revision (that is, top), which imports the .personax file, must include auto global clock promotion for clocks, resets, and clock enable signalss.
- To avoid certain routing failures, set the Fitter Preservation Level for the Top partition to Netlist Only. You may assign the setting via the Design Partitions Window or the Tcl Console.
In addition to these workarounds, take into account the following considerations:
- The pll_rom.hex file exists before compilation.
- Intel® Quartus® Prime compilation is only ever performed after the Intel® FPGA SDK for OpenCL™ Offline Compiler has embedded an OpenCL™ kernel inside the system.
- Perform Intel® Quartus® Prime compilation after you install the Intel® FPGA SDK for OpenCL™ and set the INTELFPGAOCLSDKROOT environment variable to point to the SDK installation.
- The name of the directory where the Intel® Quartus® Prime project resides must match the name field in the board_spec.xml file within the Custom Platform. The name must be case sensitive.
- The PATH or LD_LIBRARY_PATH environment variable must point to the MMD library in the Custom Platform.
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