Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

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ID 683645
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide 2. Developing Your Custom Platform 3. Stratix V Network Reference Platform Design Architecture A. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide x
1.1. Stratix V Network Reference Platform: Prerequisites 1.2. Features of the Stratix V Network Reference Platform 1.3. Contents of the Stratix V Network Reference Platform
1.1. Stratix V Network Reference Platform: Prerequisites x
1.1.1. Legacy Board Support
2. Developing Your Custom Platform x
2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
2.4. Setting up the Software Development Environment x
2.4.1. Setting Up Software Development Environment for Windows 2.4.2. Setting Up the Software Development Environment for Linux
3. Stratix V Network Reference Platform Design Architecture x
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
3.1. Host-FPGA Communication over PCIe x
3.1.1. Parameter Settings for PCIe Instantiation 3.1.2. PCIe Device Identification Registers 3.1.3. Version ID 3.1.4. Definitions of Hardware Constants in Software Header Files 3.1.5. PCIe Kernel Driver 3.1.6. SG-DMA Hardware Software
3.2. DDR3 as Global Memory for OpenCL Applications x
3.2.1. DDR3 IP Instantiation 3.2.2. DDR3 Connection to PCIe Host 3.2.3. DDR3 Connection to OpenCL Kernel
3.5. Implementation of UDP Cores as OpenCL Channels x
3.5.1. QuickUDP IP Instantiation 3.5.2. QuickUDP Configuration via PCIe-Based Host 3.5.3. QuickUDP Connection to OpenCL Kernel
3.6. FPGA System Design x
3.6.1. Clocks 3.6.2. Resets 3.6.3. Floorplan 3.6.4. Global Routing 3.6.5. Pipelining 3.6.6. Encrypted IPs
3.7. Guaranteed Timing Closure x
3.7.1. Supply the Kernel Clock 3.7.2. Guarantee Kernel Clock Timing 3.7.3. Provide a Timing-Closed Post-Fit Netlist
3.9. Connection to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe s5_net to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the s5_net Hardware to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow x
3.10.1. CvP 3.10.2. Flash 3.10.3. Defining the Contents of the fpga.bin File
3.10.1. CvP x
3.10.1.1. Replacing FPGA Core Logic via CvP Programming 3.10.1.2. Specifying Configuration via PCI Express Options 3.10.1.3. Base versus CvP Update Revisions in CvP Programming
3.12. OpenCL Utilities Implementation x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide
2. Developing Your Custom Platform
3. Stratix V Network Reference Platform Design Architecture
A. Document Revision History

3.1.6. SG-DMA

The acl_dma_core.qsys file within the OpenCL™ SGDMA Controller IP encapsulates and parameterizes the modular scatter-gather SG-DMA hardware. The board.qsys system instantiates the acl_dma.qsys file within the OpenCL SGDMA Controller IP. For more information on SG-DMA, visit the Modular SG-DMA page on the Altera® Wiki website.

Hardware

The acl_dma_core.qsys file presents slave ports for the control and status registers (dma_csr) and the descriptors (dma_descriptors). It also provides separate masters for read and write operations. The acl_dma.qsys Platform Designer (Standard) System File adds the following features:

  • An address span extender for non-DMA memory accesses
  • A merged read/write master

The merged read/write master issues constant bursts of size 16, resulting in a 1/16 efficiency degradation from sharing the time interface. However, the bandwidth of this unit exceeds the bandwidth of the PCIe® connection by more than this amount. Therefore, there is no observable host-to-memory bandwidth degradation.

Software

When the MMD receives a request for data transfer, it uses DMA when both of the following conditions are true:

  1. The transfer size is bigger than 1024 bytes.
  2. There are 64-byte alignments with the starting addresses for both the host buffer and the device offset.

Perform the following tasks to carry out a DMA transfer:

  1. Check if there are remaining bytes to be sent.
  2. Unpin the memory from the previous transfer.
  3. Pin the memory for the new transfer.
  4. Set up the Address Translation Tables on the PCIe.
  5. Create and send the DMA descriptor.
  6. Wait until the DMA finishes and then repeat Step 1.
Attention: For the Stratix® V Network Reference Platform, this implementation is in the Linux kernel driver in the <path_to_s5_net>/linux64/driver/aclpci_dma.c file. For Windows systems, the implementation is in the <path_to_s5_net>\source\host\mmd\acl_pcie_dma_windows.cpp file.
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