Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Public
Document Table of Contents

2.7. Connecting the Memory

Calibrate the external memory IP and controllers in your Custom Platform, and connect them to the host.
  1. In your Custom Platform, instantiate your external memory IP based on the information in the DDR3 as Global Memory for OpenCL Applications section.
  2. Update the <your_custom_platform_name>/hardware/<board_name>/board_spec.xml file to reflect the modifications.
  3. Remove the boardtest hardware configuration file that you created during the integration of your Custom Platform with the Intel® FPGA SDK for OpenCL™ .
  4. Recompile the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/boardtest.cl kernel source file.
    The environment variable INTELFPGAOCLSDKROOT points to the location of the SDK installation.
  5. Reprogram the FPGA with the new boardtest hardware configuration file and then reboot your machine.
  6. Modify the MMD source code to exit after checking the UniPHY status register in the function wait_for_uniphy. Rebuild the MMD software.
  7. Run the aocl diagnose utility command and confirm that the host reads back both the version ID and the value 0 from the uniphy_status component.
    The utility should return the message Uniphy are calibrated.
  8. Consider using the Signal Tap logic analyzer to confirm the successful calibration of all memory controllers.