Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide
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3.2.1. DDR3 IP Instantiation
IP Parameter | Configuration Setting |
---|---|
Timing Parameters | As per the computing card's data specifications. |
Phase-locked loop (PLL)/delay-locked loop (DLL) Sharing | s5_net is configured such that both memory controllers can share the same PLL and DLL. |
Avalon® Width Power of 2 | Currently, OpenCL™ does not support non-power-of-2 bus widths. As a result, s5_net uses the option that forces the DDR3 controller to power of 2. Use the additional pins of this x72 core for error checking between the memory controller and the physical module. |
Byte Enable Support | OpenCL™ requires byte-level granularity to all memories; therefore, byte-enable support is necessary in the core. |
Performance | Enabling reordering and a deeper command queue look-ahead depth might provide increased bandwidth for some OpenCL kernels. For a target application, adjust these and other parameters as necessary. |
Debug | Debug is disabled for production. |
After you instantiate the UniPHY IP, you typically need to run the <variation_name>_pin_assignments.tcl Tcl script to add additional constraints to the Intel® Quartus® Prime project. For more information on this process, refer to the Adding Pins and DQ Group Assignments section in Volume 2 of the External Memory Interface Handbook.