Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

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ID 683645
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide 2. Developing Your Custom Platform 3. Stratix V Network Reference Platform Design Architecture A. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide x
1.1. Stratix V Network Reference Platform: Prerequisites 1.2. Features of the Stratix V Network Reference Platform 1.3. Contents of the Stratix V Network Reference Platform
1.1. Stratix V Network Reference Platform: Prerequisites x
1.1.1. Legacy Board Support
2. Developing Your Custom Platform x
2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
2.4. Setting up the Software Development Environment x
2.4.1. Setting Up Software Development Environment for Windows 2.4.2. Setting Up the Software Development Environment for Linux
3. Stratix V Network Reference Platform Design Architecture x
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
3.1. Host-FPGA Communication over PCIe x
3.1.1. Parameter Settings for PCIe Instantiation 3.1.2. PCIe Device Identification Registers 3.1.3. Version ID 3.1.4. Definitions of Hardware Constants in Software Header Files 3.1.5. PCIe Kernel Driver 3.1.6. SG-DMA
3.2. DDR3 as Global Memory for OpenCL Applications x
3.2.1. DDR3 IP Instantiation 3.2.2. DDR3 Connection to PCIe Host 3.2.3. DDR3 Connection to OpenCL Kernel
3.5. Implementation of UDP Cores as OpenCL Channels x
3.5.1. QuickUDP IP Instantiation 3.5.2. QuickUDP Configuration via PCIe-Based Host 3.5.3. QuickUDP Connection to OpenCL Kernel
3.6. FPGA System Design x
3.6.1. Clocks 3.6.2. Resets 3.6.3. Floorplan 3.6.4. Global Routing 3.6.5. Pipelining 3.6.6. Encrypted IPs
3.7. Guaranteed Timing Closure x
3.7.1. Supply the Kernel Clock 3.7.2. Guarantee Kernel Clock Timing 3.7.3. Provide a Timing-Closed Post-Fit Netlist
3.9. Connection to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe s5_net to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the s5_net Hardware to the Intel® FPGA SDK for OpenCL™ Board Device Global Memory Channels Interfaces Compile
3.10. FPGA Programming Flow x
3.10.1. CvP 3.10.2. Flash 3.10.3. Defining the Contents of the fpga.bin File
3.10.1. CvP x
3.10.1.1. Replacing FPGA Core Logic via CvP Programming 3.10.1.2. Specifying Configuration via PCI Express Options 3.10.1.3. Base versus CvP Update Revisions in CvP Programming
3.12. OpenCL Utilities Implementation x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide
2. Developing Your Custom Platform
3. Stratix V Network Reference Platform Design Architecture
A. Document Revision History

3.9.2. Describe the s5_net Hardware to the Intel® FPGA SDK for OpenCL™

The Stratix® V Network Reference Platform includes a board_spec.xml file that describes the hardware to the Intel® FPGA SDK for OpenCL™ in the contexts described below.

Board

The version attribute of the board element must match the Intel® Quartus® Prime software version you use to develop the Custom Platform.

Device

The device section contains the name of the device model file available in the INTELFPGAOCLSDKROOT/share/models/dm directory of the SDK and in the board spec.xml file. The used_resources element accounts for all logic outside of the kernel. The value of used_resources equals the difference between the number of adaptive logic modules (ALMs) used in final placement and the number of ALMs used for registers. You can derive this value from the Partition Statistic section of the Fitter report. Consider the following ALM categories within an example Fitter report: 

; Statistic                                               ;
+----------------------------------------------------------
; Logic utilization (ALMs needed/total ALMs on device)    ;
; ALMs needed [=A-B+C]                                    ;
;   [A] ALMs used in final placement [=a+b+c+d]           ;
;     [a] ALMs used for LUT logic and registers           ;
;     [b] ALMs used for LUT logic                         ;
;     [c] ALMs used for registers                         ;
;     [d] ALMs used for memory (up to half of total ALMs) ;
;   [B] Estimate of ALMs recoverable by dense packing     ;
;   [C] Estimate of ALMs unavailable [=a+b+c+d]           ;
;     [a] Due to location constrained logic               ;
;     [b] Due to LAB-wide signal conflicts                ;
;     [c] Due to LAB input limits                         ;
;     [d] Due to virtual I/Os                             ;

The value of used_resources equals ALMs used in final placement minus ALMs used for registers (that is, [A] - [c]).

Global Memory

In the board_spec.xml file, there are separate global_mem sections for DDR and QDR memory, namely DDR and QDR, respectively. Assign DDR and QDR to the name attribute of the global_mem element. The board instance in Platform Designer (Standard) provides all of these interfaces; therefore, board is specified in the name attribute of all the interface elements within global_mem.

  • DDR

    Because DDR memory serves as the default memory for the board that s5_net targets, its address attribute begins at zero. Its config_ddr is 0x018 to match the memorg conduit used to connect to the corresponding Memory Bank Divider for DDR.

    Attention: The width and burst sizes must match the parameters in the Memory Bank Divider for DDR (memory_bank_divider_0).

  • QDR

    The QDR section begins its address attribute directly after the DDR address space stops, and its config_addr is 0x100, as indicated in the name of its memorg conduit. Because QDR provides separate read and write ports, each port is described to the Intel® FPGA SDK for OpenCL™ Offline Compiler in a separate port attribute.

    As discussed in the Pipelining section, the addpipe option is necessary because the QDR kernel interfaces are at the top of the FPGA and the rest of the kernel interface signals are along the bottom of the device.

    Attention: The width and burst sizes must match the parameters in the Memory Bank Divider for QDR (memory_bank_divider_1).

Channels

The channels section describes the send and receive Avalon®-ST channels for each of the UDP cores, for a total of four 256-bit Intel® FPGA SDK for OpenCL™ Offline Compiler channels. These channel interfaces originate in the hardware from the udp_0 instance. Therefore, udp_0 is specified in all the name attributes. The port attribute identifies the name of the Platform Designer (Standard) interface to which a channel connects. The chan_id attribute is the identifier with which the SDK user declares the channel.

Interfaces

The interfaces section describes kernel clocks, reset, CRA, and snoop interfaces. The Memory Bank Divider for the default memory (in this case, memory_bank_divider_0) exports the snoop interface described in the interfaces section. The width of the snoop interface should match the width of the corresponding streaming interface.

Compile

The compile section describes your Intel® Quartus® Prime project and provides the commands necessary to generate and synthesize the RTL in your design. In addition, it explicitly registers itself with the Automigration platform. If you derive your Custom Platform design from s5_net, set the platform_type parameter of the auto_migrate attribute to s5_net.

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