Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Public
Document Table of Contents

3.1.1. Parameter Settings for PCIe Instantiation

The Stratix® V Network Reference Platform instantiates the Stratix V PCIe® hard IP to implement a host-to-device connection over PCIe.

Dependencies

  • Stratix V hard IP for PCI Express
  • For Windows systems, Jungo WinDriver
Table 3.  Highlights of the Stratix V PCIe hard IP Configuration Settings
Parameter Setting
Lanes Lane rate: Gen2 (5.0 Gbps)

Number of lanes: x8

Note: This setting is the fastest configuration that can support CvP.
Rx buffer credit allocation Low
Note: This setting is derived experimentally.
Enable configuration via the PCIe link On

Click the check box to enable the setting.

Base Address Registers (BARs) The design uses only a single BAR (BAR 0).
Address Translation Tables Number of address pages: 256
Note: This setting is derived experimentally.

Size of address pages: 12 bits

Important: The number and size of the address pages must match the values in the MMD layer.