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2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
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3.1.1. Parameter Settings for PCIe Instantiation
The Stratix® V Network Reference Platform instantiates the Stratix V PCIe® hard IP to implement a host-to-device connection over PCIe.
Dependencies
- Stratix V hard IP for PCI Express
- For Windows systems, Jungo WinDriver
Parameter | Setting |
---|---|
Lanes | Lane rate: Gen2 (5.0 Gbps) Number of lanes: x8
Note: This setting is the fastest configuration that can support CvP.
|
Rx buffer credit allocation | Low
Note: This setting is derived experimentally.
|
Enable configuration via the PCIe link | On Click the check box to enable the setting. |
Base Address Registers (BARs) | The design uses only a single BAR (BAR 0). |
Address Translation Tables | Number of address pages: 256
Note: This setting is derived experimentally.
Size of address pages: 12 bits
Important: The number and size of the address pages must match the values in the MMD layer.
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