Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

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ID 683645
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide 2. Developing Your Custom Platform 3. Stratix V Network Reference Platform Design Architecture A. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide x
1.1. Stratix V Network Reference Platform: Prerequisites 1.2. Features of the Stratix V Network Reference Platform 1.3. Contents of the Stratix V Network Reference Platform
1.1. Stratix V Network Reference Platform: Prerequisites x
1.1.1. Legacy Board Support
2. Developing Your Custom Platform x
2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
2.4. Setting up the Software Development Environment x
2.4.1. Setting Up Software Development Environment for Windows 2.4.2. Setting Up the Software Development Environment for Linux
3. Stratix V Network Reference Platform Design Architecture x
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
3.1. Host-FPGA Communication over PCIe x
3.1.1. Parameter Settings for PCIe Instantiation 3.1.2. PCIe Device Identification Registers 3.1.3. Version ID 3.1.4. Definitions of Hardware Constants in Software Header Files 3.1.5. PCIe Kernel Driver 3.1.6. SG-DMA
3.2. DDR3 as Global Memory for OpenCL Applications x
3.2.1. DDR3 IP Instantiation 3.2.2. DDR3 Connection to PCIe Host 3.2.3. DDR3 Connection to OpenCL Kernel
3.5. Implementation of UDP Cores as OpenCL Channels x
3.5.1. QuickUDP IP Instantiation 3.5.2. QuickUDP Configuration via PCIe-Based Host 3.5.3. QuickUDP Connection to OpenCL Kernel
3.6. FPGA System Design x
3.6.1. Clocks 3.6.2. Resets 3.6.3. Floorplan 3.6.4. Global Routing 3.6.5. Pipelining 3.6.6. Encrypted IPs
3.7. Guaranteed Timing Closure x
3.7.1. Supply the Kernel Clock 3.7.2. Guarantee Kernel Clock Timing 3.7.3. Provide a Timing-Closed Post-Fit Netlist
3.9. Connection to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe s5_net to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the s5_net Hardware to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow x
3.10.1. CvP 3.10.2. Flash 3.10.3. Defining the Contents of the fpga.bin File
3.10.1. CvP x
3.10.1.1. Replacing FPGA Core Logic via CvP Programming 3.10.1.2. Specifying Configuration via PCI Express Options 3.10.1.3. Base versus CvP Update Revisions in CvP Programming
3.12. OpenCL Utilities Implementation x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide
2. Developing Your Custom Platform
3. Stratix V Network Reference Platform Design Architecture
A. Document Revision History

3.10.1.2. Specifying Configuration via PCI Express Options

To enable Configuration via Protocol programming of the FPGA core logic, specify the configuration via PCIe™ options in the Intel® Quartus® Prime software.
  1. In the Stratix V HIP for PCI Express parameter editor GUI, under System Settings, select Enable configuration via the PCIe link to enable CvP on the PCIe IP.
  2. Include the following INI settings in the quartus.ini file: 
    skip_hssi_gen3_pcie_hip_cvp_enable_rule = on
skip_hssi_gen3_pcie_hip_hip_hard_reset_rule = on
skip_hssi_gen3_pcie_hip_hrdrstctrl_en_rule = on
  3. In the Intel® Quartus® Prime software, click Assignments > Device > Device and Pin Options to open the Device and Pin Options dialog box.
  4. Under General, select Enable autonomous PCIe HIP mode.
  5. Under CvP Settings, perform the following tasks:
    1. Set Configuration via Protocol to Core update.
    2. Select Enable CvP_CONFDONE pin.
    3. Select Enable open drain on CvP_CONFDONE pin.

The PCIe core must have the force_hrc parameter set to a value of 1 in the board.qsys file. Because you cannot set this parameter using the Platform Designer (Standard) GUI, you must save and exit Platform Designer (Standard), and then edit the setting in the board.qsys file.

Attention:

Depending on whether the PCIe core is used in the base or CvP revision, additional modifications to the PCIe controller behavior might be necessary. An additional multpersona partition named cvp_update_reset_partition is implemented to work in conjunction with the following file edits:

  • Replacement of altpcie_sv_hip_ast_hwtcl.v and altpcie_hip_256_pipen1b.v in the <path_to_OpenCL_kernel_filename_directory>/system/synthesis/submodules directory.
  • Addition of cvp_update_reset.v (for base revision) and cvp_update_reset_zero.v (for CvP update revision) in the <path_to_OpenCL_kernel_filename_directory>/system/synthesis/submodules directory.

After Platform Designer (Standard) Verilog generation and before launching the Intel® Quartus® Prime compilation, the <path_to_s5_net>/hardware/s5_net/scripts/pre_flow.tcl Tcl script performs these file edits automatically. The following Verilog source files reside in the INTELFPGAOCLSDKROOT/ip/board/migrate/cvpupdatefix directory, where INTELFPGAOCLSDKROOT points to the Intel® FPGA SDK for OpenCL™ installation directory:

  • altpcie_sv_hip_ast_hwtcl.v
  • altpcie_hip_256_pipen1b.v
  • cvp_update_reset.v
  • cvp_update_reset_zero.v
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