Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Public
Document Table of Contents

3.4. Host Connection to OpenCL Kernels

The PCIe® host needs to pass commands and arguments to the OpenCL™ kernels via the control register access (CRA) Avalon® slave port that each OpenCL kernel generates. The OpenCL Kernel Interface component exports an Avalon master interface (kernel_cra) that connects to this slave port. The OpenCL Kernel Interface component also generates the kernel reset (kernel_reset) that resets all logic in the kernel clock domain.

The Stratix® V Network Reference Platform instantiates the OpenCL Kernel Interface component and sets the Number of global memory systems parameter to 2. The parameter setting is 2 because s5_net has DDR and QDR memories. Below is a list of connection settings in s5_net:

  • For the default DDR memory, the generated memorg_host0x018 conduit must connect to the DDR bank divider (memory_bank_divider_0).
  • For the default DDR memory, the config_addr attribute in the board_spec.xml file must be set to 0x018.
  • For the QDR memory, the memorg_host0x100 conduit must connect to the QDR bank divider (memory_bank_divider_1).
  • For the QDR memory, the config_addr attribute in the board_spec.xml file must be set to 0x100.