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2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
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3.4. Host Connection to OpenCL Kernels
The PCIe® host needs to pass commands and arguments to the OpenCL™ kernels via the control register access (CRA) Avalon® slave port that each OpenCL kernel generates. The OpenCL Kernel Interface component exports an Avalon master interface (kernel_cra) that connects to this slave port. The OpenCL Kernel Interface component also generates the kernel reset (kernel_reset) that resets all logic in the kernel clock domain.
The Stratix® V Network Reference Platform instantiates the OpenCL Kernel Interface component and sets the Number of global memory systems parameter to 2. The parameter setting is 2 because s5_net has DDR and QDR memories. Below is a list of connection settings in s5_net:
- For the default DDR memory, the generated memorg_host0x018 conduit must connect to the DDR bank divider (memory_bank_divider_0).
- For the default DDR memory, the config_addr attribute in the board_spec.xml file must be set to 0x018.
- For the QDR memory, the memorg_host0x100 conduit must connect to the QDR bank divider (memory_bank_divider_1).
- For the QDR memory, the config_addr attribute in the board_spec.xml file must be set to 0x100.