Visible to Intel only — GUID: ewa1404930688066
Ixiasoft
Visible to Intel only — GUID: ewa1404930688066
Ixiasoft
3.1.6. SG-DMA
Hardware
The acl_dma_core.qsys file presents slave ports for the control and status registers (dma_csr) and the descriptors (dma_descriptors). It also provides separate masters for read and write operations. The acl_dma.qsys Platform Designer (Standard) System File adds the following features:
- An address span extender for non-DMA memory accesses
- A merged read/write master
The merged read/write master issues constant bursts of size 16, resulting in a 1/16 efficiency degradation from sharing the time interface. However, the bandwidth of this unit exceeds the bandwidth of the PCIe® connection by more than this amount. Therefore, there is no observable host-to-memory bandwidth degradation.
Software
When the MMD receives a request for data transfer, it uses DMA when both of the following conditions are true:
- The transfer size is bigger than 1024 bytes.
- There are 64-byte alignments with the starting addresses for both the host buffer and the device offset.
Perform the following tasks to carry out a DMA transfer:
- Check if there are remaining bytes to be sent.
- Unpin the memory from the previous transfer.
- Pin the memory for the new transfer.
- Set up the Address Translation Tables on the PCIe.
- Create and send the DMA descriptor.
- Wait until the DMA finishes and then repeat Step 1.