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2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
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Ixiasoft
2. Developing Your Custom Platform
Use the tools available in the Stratix® V Network Reference Platform and the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit together to create your own Custom Platform.
Developing your Custom Platform requires in-depth knowledge of the contents in the following documents and tools:
- Intel® FPGA SDK for OpenCL™ Custom Platform User Guide
- Contents of the Custom Platform Toolkit
- Stratix V Network Reference Platform Porting Guide
- Documentation for all the Intel® FPGA IP in your Custom Platform
- Intel® FPGA SDK for OpenCL™ Getting Started Guide
- Intel® FPGA SDK for OpenCL™ Programming Guide
In addition, you must independently verify all the hard IPs on your computing card (for example, PCIe® controllers, DDR3 external memory, and Ethernet).
Section Content
Initializing Your Custom Platform
Removing Unused Hardware
Integrating Your Custom Platform with the Intel FPGA SDK for OpenCL
Setting up the Software Development Environment
Building the Software in Your Custom Platform
Establishing Host Communication
Connecting the Memory
Integrating an OpenCL Kernel
Programming Your FPGA Quickly Using CvP
Guaranteeing Timing Closure
Troubleshooting